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order number: 309823, revision: 003 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet product features the intel strataflash ? cellular memory (m18) is the 5 th generation intel strataflash ? memory with multi-level cell (mlc) technology. it provides high performance, low-power synchronous- burst read mode and asynchronous read mode at 1.8 v. it features flexible, multi-partition read- while-program and read-while-erase capability, enabling background programming or erasing in one partition simultaneously with code execution or data reads in another partition. this dual operation architecture also allows two processors to interleave code operations while program and erase operations take place in the background. the eight partitions allow flexibility for system designers to choose the size of the code and data segments. the intel strataflash ? cellular memory (m18) is manufactured using intel 90 nm etox? ix process technology and is available in industry-standard chip-scale packaging. high performance read, program and erase ? 96 ns initial access for reads ? 512-mbit device: 108 mhz with zero wait-state synchronous burst reads: 7 ns clock-to-data output ? 256-mbit device: 133 mhz with zero wait-state synchronous burst reads: 5.5 ns clock-to-data output ? 8-, 16-, and continuous-word synchronous- burst ? programmable wait configuration ? customer-configurable output driver impedance ? buffered enhanced factory programming (befp): 2.1 s/byte (typ) ? 1.8 v low-power buffered programming: 2.1 s/byte (typ) ? block erase: 0.9 s per block (typ) architecture ? 16-bit wide data bus ? multi-level cell technology ? symmetrically blocked array architecture ? 256-kbyte erase blocks ? 512-mb device: eight 64-mbit partitions ? 256-mb device: eight 32-mbit partitions ? four additional 8-kbyte extended flash array (efa) blocks ? read-while-program and read-while-erase ? status register for partition and device status ? blank check feature quality and reliability ? expanded temperature: ?30 c to +85 c ? minimum 100,000 erase cycles per block ? etox? ix process technology (90 nm) power ? core voltage: 1.7 v - 2.0 v ? i/o voltage: 1.7 v - 2.0 v ? standby current: 50 a (typ) ? deep power-down mode: 2 a (typ) ? automatic power savings mode ? 16-word synchronous-burst read current: 23 ma (typ) software ? 20 s (typ) program suspend ? 20 s (typ) erase suspend ? intel? flash data integrator optimized ? basic command set (bcs) and extended command set (ecs) compatible ? common flash interface (cfi) security ? otp registers: ? 64 unique pre-programmed bits ? 64 user-programmable bits ? additional 2048 user-programmable bits ? absolute write protection with v pp = gnd ? power-transition erase/program lockout ? individual zero-latency block locking ? individual block lock-down density and packaging ? density: 512 mbit, 256 mbit ? address-data multiplexed and non-multiplexed ? x16d (105-ball) flash scsp package ? x16c (107-ball) flash scsp package ? 0.8 mm solder-ball pitch lead-free
23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 2 order number: 309823, revision: 003 information in this document is provided in connection with intel products. no li cense, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assu mes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel product s including liability or warranties relating to fitness for a particular purpose, merchantability, or infringeme nt of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. this document contains information on products in the design phase of development. the information here is subject to change wi thout notice. do not finalize a design with this information. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com . copyright ? 2006, intel corporation * other names and brands may be claimed as the property of others.
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 3 contents 1.0 introduction ............................................................................................................................... .....7 1.1 document purpose ............................................................................................................ .7 1.2 nomenclature ................................................................................................................ .....7 1.3 acronyms.................................................................................................................... ........7 1.4 conventions................................................................................................................. .......8 2.0 functional overview .....................................................................................................................9 2.1 product description ......................................................................................................... ... 9 2.2 configuration and memory map ......................................................................................... 9 2.2.1 extended flash array .......................................................................................... 11 3.0 package information ...................................................................................................................13 4.0 ballout and signal descriptions ................................................................................................ 17 4.1 signal ballouts x16d ........................................................................................................ 17 4.1.1 x16d (105-ball) ballout, non-mux ....................................................................... 17 4.1.2 x16d ad-mux (105-ball) ballout.......................................................................... 18 4.2 signal descriptions x16d ................................................................................................. 19 4.3 signal ballouts x16c ........................................................................................................ 23 4.3.1 x16c (107-ball) ballout, non-mux ....................................................................... 23 4.3.2 x16c ad-mux (107-ball) ballout.......................................................................... 24 4.4 signal descriptions x16c ................................................................................................. 25 5.0 maximum ratings and operating conditions ...........................................................................29 5.1 absolute maximum ratings .............................................................................................. 29 5.2 operating conditions ........................................................................................................ 30 6.0 electrical characteristics ............................................................................................................31 6.1 dc current specifications ................................................................................................ 31 6.2 dc voltage specifications ................................................................................................ 33 6.3 capacitance................................................................................................................. .....33 7.0 nor flash ac characteristics ...................................................................................................34 7.1 ac test conditions.......................................................................................................... .35 7.2 read specifications ......................................................................................................... .36 7.2.1 timings: non mux device, asynchronous read .................................................40 7.2.2 timings: non mux device, synchronous read 108 mhz, 512 mb......................41 7.2.3 timings: non mux device, synchronous read 133 mhz, 256 mb......................42 7.2.4 timings: ad-mux device, asynchronous read................................................... 45 7.2.5 timings: ad-mux device, synchronous read 108 mhz, 512 mb ....................... 45 7.2.6 timings: ad-mux device, synchronous read 133 mhz, 256 mb ....................... 47 7.3 write specifications ........................................................................................................ .. 49 7.3.1 timings: non mux device, asynchronous write.................................................. 50 7.3.2 timings: non mux device, synchronous write 108 mhz, 512 mb ......................52 7.3.3 timings: non mux device, synchronous write 133 mhz, 256 mb ......................54 7.3.4 timings: ad-mux device, asynchronous write ................................................... 55 7.3.5 timings: ad-mux device, synchronous write 108 mhz, 512 mb ....................... 56
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 4 order number: 309823, revision: 003 7.3.6 timings: ad-mux device, synchronous write 133 mhz, 256 mb ....................... 57 7.4 program and erase characteristics.................................................................................. 59 7.5 reset specifications ........................................................................................................ .60 7.6 deep power down specifications .................................................................................... 61 8.0 nor flash bus interface ............................................................................................................ 62 8.1 bus reads ................................................................................................................... ..... 62 8.1.1 asynchronous single-word reads ........................................................................ 63 8.1.2 asynchronous page mode (non-multiplexed devices only) ................................ 63 8.1.3 synchronous burst mode .................................................................................... 63 8.1.3.1 wait operation ................................................................................... 64 8.2 bus writes .................................................................................................................. ...... 64 8.3 reset ....................................................................................................................... ......... 64 8.4 deep power-down .......................................................................................................... 64 8.5 standby ..................................................................................................................... ....... 65 8.6 output disable.............................................................................................................. .... 65 8.7 bus cycle interleaving...................................................................................................... 65 8.7.1 read operation during program buffer fill.......................................................... 66 8.8 read-to-write and write-to-read bus transitions ........................................................... 66 8.8.1 write to asynchronous read transition................................................................. 66 8.8.2 write to synchronous read transition ................................................................... 66 8.8.3 asynchronous/synchronous read to write transition ........................................... 67 8.8.4 bus write with active clock................................................................................... 67 9.0 nor flash operations ................................................................................................................ 68 9.1 initialization.............................................................................................................. ......... 68 9.1.1 power-up/down characteristics.......................................................................... 68 9.1.2 reset characteristics .......................................................................................... 68 9.1.3 power supply decoupling ................................................................................... 69 9.2 status register ............................................................................................................. .... 69 9.2.1 clearing the status register................................................................................ 70 9.3 read configuration register ............................................................................................ 71 9.3.1 latency count ..................................................................................................... 72 9.3.2 programming the rcr ........................................................................................ 73 9.4 enhanced configuration register .................................................................................... 74 9.4.1 output driver control .......................................................................................... 75 9.4.2 programming the ecr ....................................................................................... 75 9.5 read operations ............................................................................................................. .76 9.5.1 read array .......................................................................................................... 76 9.5.2 read status register .......................................................................................... 77 9.5.3 read device information ..................................................................................... 77 9.5.4 cfi query ............................................................................................................ 78 9.5.5 read extended flash array (efa) ..................................................................... 78 9.6 programming modes ........................................................................................................ 78 9.6.1 control mode ....................................................................................................... 79 9.6.2 object mode ........................................................................................................ 80 9.7 programming operations ................................................................................................. 82 9.7.1 single-word programming .................................................................................. 82 9.7.2 buffered programming ........................................................................................ 83 9.7.3 buffered enhanced factory programming (befp) ............................................ 84
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 5 9.7.3.1 setup phase ........................................................................................85 9.7.3.2 program/verify phase.......................................................................... 85 9.7.3.3 exit phase............................................................................................85 9.7.4 efa word programming .....................................................................................86 9.8 block erase operations .................................................................................................... 86 9.9 blank check operation .................................................................................................... 87 9.10 suspend and resume ......................................................................................................88 9.11 simultaneous operations ................................................................................................. 90 9.12 security................................................................................................................... ..........91 9.12.1 block locking....................................................................................................... 91 9.12.2 one-time programmable (otp) registers ......................................................... 92 9.12.3 global main-array protection...............................................................................94 appendix a device command codes .......................................................................................... 95 appendix b device id codes ........................................................................................................ 97 appendix c flow charts ............................................................................................................... 98 appendix d common flash interface ........................................................................................ 107 appendix e next state table ...................................................................................................... 116 appendix f additional information ............................................................................................ 123 appendix g ordering information .............................................................................................. 124
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 6 order number: 309823, revision: 003 revision history revision date revision description october 05 001 initial release 28-dec-05 002 made the following specifcations changes: initial read access speed changed to 96 ns as shown in ?high performance read, program and erase? on page 1 . revised i ccs test conditions in table 7 ?dc current specifications? on page 31 . latency count for 66 mhz changed to 7 in table 7 ?dc current specifications? on page 31 and in table 24 ?clk frequencies for lc settings? on page 73 . latency count for 108 mhz changed to 10 in table 7 ?dc current specifications? on page 31 . latency count for 133 mhz changed to 13 in table 7 ?dc current specifications? on page 31 and in table 24 ?clk frequencies for lc settings? on page 73 . revised v pp program and erase specifications and test conditions in table 7 ?dc current specifications? on page 31 . r201 t clk changed to 9.26 in table 12 ?ac read, 512 mbit, 108 mhz, vccq = 1.7 v to 2.0 v? on page 36 . r317 t vhch min changed to 2 in table 13 ?ac read, 256 mbit, 133 mhz, vccq = 1.7 v to 2.0 v? on page 38 . added data and adress valid information to table 3 ?signal descriptions for x16d / x16d ad- mux ballout? on page 19 . updated the description for the adv# signal to include 108 mhz in table 4 ?signal descriptions for x16c / x16c ad-mux ballout? on page 25 . updated the data value in the comments column of the befp confirm operation in figure 60 ?buffered efp flowchart? on page 101 . updated the address signal names to address [max:4] [a] and a[3:0] in figure 14 ?asynchronous single-word read with adv# latch? on page 40 . 23-feb-06 003 made the following specification updates: corrected two typographical errors as follows: 512 kb changed to 512 bytes and 1 kb changed to 512 bytes in section 9.6.1, ?control mode? on page 79 . corrected one typographical error as follows: max value for r17 changed from 14 to 9 in table 12 ?ac read, 512 mbit, 108 mhz, vccq = 1.7 v to 2.0 v? on page 36 . updated the package in figure 3 ?mechanical specificati ons for x16d (105-ball) package (8x10x1.4 mm)? on page 13 . changed wording from ?power transitions? to ?signal transitions? in notes for table 5 ?absolute maximum ratings? on page 29 . changed value for t c in notes for table 7 ?dc current specifications? on page 31 . changed wording from ?power transitions? to ?signal transitions? in notes for ta b l e 8 ?d c voltage specifications? on page 33 . changed value for t c in notes for table 9 ?capacitance? on page 33 . revised table 11 ?test configuration component value for worst case speed conditions? on page 35 . revised symbol in the symbol column for r17 in table 12 ?ac read, 512 mbit, 108 mhz, vccq = 1.7 v to 2.0 v? on page 36 . changed value for t c in notes for table 15 ?program and erase characteristics? on page 59 . revised the table 63 ?package ordering information? on page 125 as follows: changed the package of the non-mux x16d 105-ball 512 + 512 flash device to 8 x 10 x 1.4. also added the following new line item: mux x16d 105-ball 512 + 512 flash device 8 x 10 x 1.4 package.
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 7 1.0 introduction 1.1 document purpose this document describes the device interface, operations, and specifications of the intel strataflash ? cellular memory (m18) device. 1.2 nomenclature 1.3 acronyms bcs basic command set cfi common flash interface cui command user interface du don?t use ecr enhanced configuration register (flash) efa extended flash array etox eprom tunnel oxide 1.8 v refers to v cc and v ccq voltage range of 1.7 v to 2.0 v block a group of bits that erase with one erase command main array a group of 256-kb blocks used for storing code or data extended flash array a group of four 8-kb blocks outside of the main array partition a group of blocks that share common program and erase circuitry and command status register programming region an aligned 1-kb section of the main array segment a 32-byte section of the programming region byte 8 bits word 2 bytes = 16 bits kb 1024 bits kb 1024 bytes kw 1024 words mb 1,048,576 bits mb 1,048,576 bytes
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 8 number: 309823, revision: 003 fdi flash data integrator rcr read configuration register (flash) rfu reserved for future use scsp stacked chip scale package sr status register 1.4 conventions group membership brackets square brackets are used to designate group membership or to define a group of signals with a similar function, such as a[21:1]. vcc vs. v cc when referring to a signal or package-connection name, the notation used is vcc. when referring to a timing or el ectrical level, the notation used is subscripted such as v cc . device this term is used interchangeably throughout this document to denote either a particular die, or all die in the package. f[3:1]-ce#, f[2:1]-oe# this is the method used to refer to more than one chip-enable or output enable. when each is referred to individually, the reference is f1-ce# and f1-oe# (for die #1), and f2-ce# and f2-oe# (for die #2). f-vcc when referencing flash memory signals or timings, the notation used is f-vcc or f-v cc, respectively. 00ffh denotes 16-bit hexadecimal numbers 00ff 00ffh denotes 32-bit hexadecimal numbers
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 9 2.0 functional overview this section provides an overview of the device features and a detailed description of the device memory architecture. 2.1 product description the intel strataflash ? cellular memory (m18) device provides high read and write performance at low voltage on a 16-bit data bus. the flash memory device has a multi-partition architecture with read-while-program and read- while-erase capability. it supports synchronous burst reads of up to 108 mhz on 512-mb and devices and 133 mhz on 256-mbit devices. in continuous-burst mode, data can be read from the bottom to the top of memory across partition boundaries. upon initial power up or return from reset, the device defaults to asynchronous array-read mode. synchronous burst-mode reads are enabled by setting the read configuration register. in synchronous burst mode, output data is synchronized with a user-supplied clock signal. a wait signal provides easy cpu-to-flash memory synchronization. designed for low-voltage applications, the device supports read operations with v cc at 1.8 v, and erase and program operations with v pp at 1.8 v or 9.0 v. vcc and vpp can be tied together for a simple, ultra-low power design. in addition to voltage flexibility, a dedicated vpp connection provides complete data protection when v pp is less than v pplk . a status register provides status and error conditions of erase and program operations. one-time-programmable registers allows unique flash device identification that can be used to increase flash content security. also, the individual block-lock feature provides zero-latency block locking and unlocking to protect against unwanted program or erase of the array. the flash memory device offers three power savings features: automatic power savings (aps) mode, standby mode, and deep power-down (dpd) mode. the device automatically enters aps following read-cycle completion. standby is initiated when the system deselects the device by deasserting ce#. the dpd mode provides the lowest power consumption; it is enabled by setting a bit in the enhanced configuration register and entered by asserting the dpd pin. 2.2 configuration and memory map the intel strataflash ? cellular memory device features a symmetrical block architecture. the device main array is divided as follows: ? the 256-mb device has a main array of 128 blocks. there are eight 32-mb partitions, each containing 16 blocks of 256 kb. ? the 512-mb device has a main array of 256 blocks. there are eight 64-mb partitions, each containing 32 blocks of 256 kb.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 10 order number: 309823, revision: 003 flash cells within a block are organized by regions and segments. ? a block contains 256 regions of 1024 bytes that are called ?programming regions?. ? each programming region has 32 ?segments? of 32 bytes each. ? the 32 segments within the programming region are divided into two halves, ?a-half? and ?b- half?. the a-half has a3 = 0 addresses, and the b-half has a3 = 1 addresses. see table 1 for main array memory map, figure 1 for main array architecture, and figure 2 for programming region architecture for details. table 1. main array memory map 256-mbit device 512-mbit device blk # address range blk # address range partition 7 32mbit 127 0fe0000-0ffffff 64mbit 255 1fe0000-1ffffff ... ... ... ... 112 0e00000-0e1ffff 224 1c00000-1c1ffff partition 6 32mbit 111 0de0000-0dfffff 64mbit 223 1be0000-1bfffff ... ... ... ... 96 0c00000-0c1ffff 192 1800000-181ffff partition 5 32mbit 95 0be0000-0bfffff 64mbit 191 17e0000-17fffff ... ... ... ... 80 0a00000-0a1ffff 160 1400000-141ffff partition 4 32mbit 79 09e0000-09fffff 64mbit 159 13e0000-13fffff ... ... ... ... 64 0800000-081ffff 128 1000000-101ffff partition 3 32mbit 63 07e0000-07fffff 64mbit 127 0fe0000-0ffffff ... ... ... ... 48 0600000-061ffff 96 0c00000-0c1ffff partition 2 32mbit 47 05e0000-05fffff 64mbit 95 0be0000-0bfffff ... ... ... ... 32 0400000-041ffff 64 0800000-081ffff partition 1 32mbit 31 03e0000-03fffff 64mbit 63 07e0000-07fffff ... ... ... ... 16 0200000-021ffff 32 0400000-041ffff partition 0 32mbit 15 01e0000-01fffff 64mbit 31 03e0000-03fffff ... ... ... ... 0 0000000-001ffff 0 0000000-001ffff
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 11 2.2.1 extended flash array in additional to the main array, the flash device features four 8-kb extended flash array (efa) blocks. the efa block plane is not part of the main array, however it maps to a main array partition during a read, program or erase operation. see table 2 for efa block addresses. figure 1. main array architecture figure 2. programming region architecture main flash array flash block 2 5 6 p r o g r a m m i n g r e g i o n s p e r b l o c k 512 words prog region 512 words prog region flash block flash block flash block 512w address space 512 words prog region 16 words (32 byte ) 512 words (1kbyte) 512w address space 512w address space segment 0 segment 31 segment 2 segment 30 segment 1 - - 128k 128k - 128k - word 128k 128k - - word word 128k - word 128k - word 128k - word 128k - word 128k - word 128k - word 128k - word 512 words prog region flash programming region 512w address space a half (a 3 = ?0 ?) b half (a 3=?1?) 1kb (512 words) 16 b 16 b segm ent 0 segm ent 31 segm ent 2 segm ent 3 segm ent 30 segm ent 1
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 12 order number: 309823, revision: 003 table 2. extended flash array (efa) blocks memory map blk # address range 256kbit 3 0003000-0003fff 2 0002000-0002fff 1 0001000-0001fff 0 0000000-0000fff
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 13 3.0 package information the following figures show the ballout package information for the m18 device in x16c and x16d scsp ballouts. figure 3 and figure 4 shows the x16d 105-ball package, and figure 5 and figure 6 show a x16c 107-ball package. figure 3. mechanical specifications for x16d (105-ball) package (8x10x1.4 mm) dimensions symbol min nom max notes min nom max package height a 1.4 0.0551 ball height a1 0.200 0.0079 package body thickness a2 1.070 0.0421 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 9.90 10.00 10.10 0.3898 0.3937 0.3976 package body width e 7.90 8.00 8.10 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 105 105 seating plane coplanarity y 0.100 0.0039 corner to ball distance along e s1 0.700 0.800 0.900 0.0276 0.0315 0.0354 corner to ball distance along d s2 0.500 0.600 0.700 0.0197 0.0236 0.0276 note: drawing not to scale. a y a2 a1 pin 1 co rn er d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m scs p top v i ew - bal l s i de down s1 s2 e
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 14 order number: 309823, revision: 003 figure 4. mechanical specifications for x16d (105-ball) package (9x11x1.2 mm) dimensions symbol min nom max notes min nom max package height a 1.2 0.0472 ball heig ht a1 0.200 0.0079 package body thickness a2 0.860 0. 0339 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 10.90 11.00 11.10 0. 4291 0.4331 0.4370 package body width e 8.90 9.00 9.10 0. 3504 0.3543 0.3583 pitch e 0.800 0.0315 ball (lead) count n 105 105 seating plane coplanarity y 0.100 0.0039 corner to ball dis tance along e s1 1.200 1.300 1.400 0.0472 0.0512 0.0551 corner to ball dis tance along d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 note: drawing not to scale. a y a2 a1 pin 1 corner d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m top view - ball side down s1 s2 e
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 15 figure 5. mechanical specifications for x16c (107-ball) package (8x11x1.2 mm) m illimet ers inches dimensions symbol min nom max notes min nom max package height a 1.2 0.0472 ball height a1 0.200 0.0079 package body thickness a2 0.860 0.0339 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package bo dy len gth d 10.90 11.00 11.10 0.4291 0.4331 0.4370 package bo dy wid th e 7.90 8.00 8.10 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 107 107 seating plane coplanarity y 0.100 0.0039 corner to ball distance along e s1 0.700 0.800 0.900 0.0276 0.0315 0.0354 corner to ball distance along d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 note: drawing not to scale. a y a2 a1 pin 1 corner d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m top view - ball side down s1 s2 e
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 16 order number: 309823, revision: 003 figure 6. mechanical specifications for x16c (107-ball) package (8x11x1.4 mm) note: drawing not to scale. a y a2 a1 pin 1 corner d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m top view - ball side down s1 s2 e millimeters inches dimensions symbol min nom max notes min nom max package height a 1.4 0.0551 ball height a1 0.200 0.0079 package bo dy thicknes s a2 1.070 0.0421 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package bo dy leng th d 10.90 11.00 11.10 0.4291 0.4331 0.4370 package bo dy width e 7.90 8.00 8.10 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 107 107 seating plane coplanarity y 0.100 0.0039 corner to ball dis tance alon g e s1 0.700 0.800 0.900 0.0276 0.0315 0.0354 corner to ball dis tance alon g d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 17 4.0 ballout and signal descriptions this section provides ballout and signal description information for x16d (105-ball) and x16c (107-ball) packages, non-mux and ad-mux. 4.1 signal ballouts x16d 4.1.1 x16d (105-ball) ballout, non-mux figure 7. x16d (105-ball) electrical ballout, non-mux pin 1 123456789 a du a4 a6 a7 a19 a23 a24 a25 du a b a2 a3 a5 a17 a18 f-dpd a22 a26 a16 b c a1 vss vss vss d-vcc vss vss vss a15 c d a0 s-vcc d-vcc f-vcc f-adv# f-vcc d-vcc n-ale a14 d e f-wp1# we# d2-cs# depop (index) n-cle f4-ce# / a27 a21 a10 a13 e f f-wp2# d1-cs# d-cas# d-ras# depop (rfu) s-cs1# / n-re# a20 a9 a12 f g rfu f2-ce# f1-ce# d-ba0 depop (rfu) d-cke f-rst# a8 a11 g h n-ry/by# s-cs2 / n-we# f3-ce# d-ba1 d-clk# d-we# oe# d-dm1 / s-ub# d-dm0 / s-lb# h j f-vpp vccq vccq f-vcc d-clk f-vcc vccq vccq f-wait j k dq2 vss vss vss f-clk vss vss vss dq13 k l dq1 dq3 dq5 dq6 dq7 dq9 dq11 dq12 dq14 l m du dq0 d-ldqs dq4 dq8 dq10 d-udqs dq15 du m 123456789 active balls do not use de-populated balls top view - ball side down reserved for future use legend:
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 18 order number: 309823, revision: 003 4.1.2 x16d ad-mux (105-ball) ballout figure 8. x16d ad-mux (105-ball) electrical ballout pin 1 123456789 a du a4 a6 a7 a19 a23 a24 a25 du a b a2 a3 a5 a17 a18 f-dpd a22 a26 a16 b c a1 vss vss vss d-vcc vss vss vss a15 c d a0 s-vcc d-vcc f-vcc f-adv# f-vcc d-vcc n-ale a14 d e f-wp1# we# d2-cs# depop (index) n-cle f4-ce# / a27 a21 a10 a13 e f f-wp2# d1-cs# d-cas# d-ras# depop (rfu) s-cs1# / n-re# a20 a9 a12 f g rfu f2-ce# f1-ce# d-ba0 depop (rfu) d-cke f-rst# a8 a11 g h n-ry/by# s-cs2 / n-we# f3-ce# d-ba1 d-clk# d-we# oe# d-dm1 / s-ub# d-dm0 / s-lb# h j f-vpp vccq vccq f-vcc d-clk f-vcc vccq vccq f-wait j k ad2 vss vss vss f-clk vss vss vss ad13 k l ad1 ad3 ad5 ad6 ad7 ad9 ad11 ad12 ad14 l m du ad0 d-ldqs ad4 ad8 ad10 d-udqs ad15 du m 123456789 de-populated balls active balls do not use top view - ball side down reserved for future use legend:
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 19 4.2 signal descriptions x16d table 3. signal descriptions for x16d / x16d ad-mux ballout (sheet 1 of 4) symbol type signal descriptions notes address and data signals, non-mux a[max: 0] input address: global device signals. shared address inputs for all memory die during read and write operations. ? 4-gbit: amax = a27 ? 2-gbit: amax = a26 ? 1-gbit: amax = a25 ? 512-mbit: amax = a24 ? 256-mbit: amax = a23 ? 128-mbit: amax = a22 ? a[12:0] are the row and a[9:0] are the column addresses for 512-mbit lpsdram. ? a[12:0] are the row and a[8:0] are the column addresses for 256-mbit lpsdram. ? a[11:0] are the row and a[8:0] are the column addresses for 128-mbit lpsdram. unused address inputs should be treated as rfu. 1 dq[15:0] input/ output data input/outputs: global device signals. dq[15:0] are used to input commands and write- data during write cycles, and to output read-data during read cycles. during nand accesses, dq[7:0] are used to input commands, address-data, and write-data, and to output read-data. data signals are high-z when the device is deselected or its output is disabled. f-adv# input flash address valid: flash-specific signal; low-true input. during synchronous flash read operations, the addr ess is latched on the rising edge of f-adv#, or on the first rising edge of f-clk after f-adv# goes low for devices that support up to 108 mhz, or on the last rising edge of f-clk after f-adv# goes low for devices that support up to 133 mhz. in an asynchronous flash read operation, the address is latched on the rising edge of f-adv# or continuously flows through while f-adv# is low. address and data signals, ad-mux a[max:16] input address: global device signals. shared address inputs for all flash and sram memory die during read and write operations. ? 4-gbit: amax = a27 ? ?2-gbit: amax = a26 ? 1-gbit: amax = a25 ? 512-mbit: amax = a24 ? 256-mbit: amax = a23 ? 128-mbit: amax = a22 unused address inputs should be treated as rfu. 1
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 20 order number: 309823, revision: 003 ad[15:0] input / output address-data multiplexed inputs/ outputs: ad-mux flash and sram lower address and data signals; lpsdram data signals. during ad-mux flash and sram write cycles, ad[15:0] are used to input the lower address followed by commands or write-data. during ad-mux flash read cycles, ad[15:0] are used to input the lower address followed by read- data output. during lpsdram accesses, ad[15:0] are used to input commands and write-data during write cycles or to output read-data during read cycles. during nand accesses, ad[7:0] are used to input co mmands, address, or write-data, and to output read-data. ad[15:0] are high-z when the flash or sr am is deselected or its output is disabled. f-adv# input flash address valid: flash-specific signal; low-true input. during synchronous flash read operations, the address is latched on the rising edge of f-adv#, or on the first rising edge of f-clk after f-adv# goes low for devices that support up to 108 mhz, or on the last rising edge of f-clk after f-adv# goes low for devices that support up to 133 mhz. in an asynchronous flash read operation, the add ress is latched on the rising edge of f-adv#. control signals f[4:1]-ce# input flash chip enable: flash-specific signal; low-true input. when low, f-ce# selects the associated flash me mory die. when high, f-ce# deselects the associated flash die. flash die power is reduced to standby levels, and its data and f-wait outputs are placed in a high-z state. ? f1-ce# is dedicated to flash die #1. ? f[4:2]-ce# are dedicated to flash die #4 through #2, respectively, if present. otherwise, any unused flash chip enable should be treated as rfu. ? for nor/nand stacked device, f1-ce# selects nor die #1, f2-ce# selects nor die #2 while f4-ce# selects nand die #1 and nand die #2 using virtual chip-select scheme, f3-ce# selects nand die #3 if present. 1 f-clk input flash clock: flash-specific signal; rising active-edge input. f-clk synchronizes the flash with the syst em clock during synchronous operations. d-clk input lpsdram clock: lpsdram-specific signal; rising active-edge input. d-clk synchronizes the lpsdram and ddr lpsdram with the system clock. 2 d-clk# input ddr lpsdram clock: ddr lpsdram-specific signal; falling active-edge input. d-clk# synchronizes the ddr lpsdram with the system clock. 2 oe# input output enable: flash- and sram-specific signal; low-true input. when low, oe# enables the output drivers of the selected flash or sram die. when high, oe# disables the output drivers of the selected flash or sram die and places the output drivers in high-z. f-rst# input flash reset: flash-specific signal; low-true input. when low, f-rst# resets internal operations an d inhibits writes. when high, f-rst# enables normal operation. f-wait output flash wait: flash -specific signal; configurable-true output. when asserted, f-wait indicates invalid output data. f-wait is driven whenever f-ce# and oe# are low. f-wait is high-z whenever f-ce# or oe# is high. we# input write enable: flash- and sram-specific signal; low-true input. when low, we# enables write operations for the enabled flash or sram die. 4 d-we# input lpsdram write enable: lpsdram-specific signal; low-true input. d-we#, together with a[max:0], d-ba[1:0], d-cke, d-cs#, d-cas#, and d-ras#, define the lpsdram command or operation. d-we# is sampled on the rising edge of d-clk. 2 table 3. signal descriptions for x16d / x16d ad-mux ballout (sheet 2 of 4) symbol type signal descriptions notes
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 21 f-wp[2:1]# input flash write protect: flash-specific signals; low-true inputs. when low, f-wp# enables the lock-down mechanism. when high, f-wp# overrides the lock-down function, enabling locked-down blocks to be unlocked with the unlock command. ? f-wp1# is dedicated to flash die #1. ? f-wp2# is common to all other flash dies, if present. otherwise it is rfu. ? for nor/nand stacked device, f-wp1# selects all nor dies, while f-wp2# selects all nand dies. f-dpd input flash deep power-down: flash-specific signal; configurable-true input. when enabled in the ecr, f-dpd is used to enter and exit deep power-down mode. n-cle input nand command latch enable: nand-specific signal; high-true input. when high, n-cle enables commands to be latched on the rising edge of n-we#. 2 n-ale input nand address latch enable: nand-specific signal; high-true input. when high, n-ale enables addresses to be latched on the rising edge of n-we#. 2 n-re# input nand read enable: nand-specific signal; low-true input. when low, n-re# enables the output drivers of the selected nand die. when high, n-re# disables the output drivers of the selected nand die and places the output drivers in high-z. 2,5 n-ry/by# output nand ready/busy: nand-specific signal; low-true output. when low, n-ry/by# indicates the nand is busy performing a read, program, or erase operation. when high, n-ry/by# indicates the nand device is ready. 2 n-we# input nand write enable: nand-specific signal; low-true input. when low, n-we# enables write operations for the enabled nand die. 2,6 d-cke input lpsdram clock enable: lpsdram-specific signal; high-true input. when high, d-cke indicates that the next d-clk edge is valid. when low, d-cke indicates that the next d-clk edge is invalid and the selected lpsdram die is suspended. 2 d-ba[1:0] input lpsdram bank select: lpsdram-specific input signals. d-ba[1:0] selects one of four banks in the lpsdram die. 2 d-ras# input lpsdram row address strobe: lpsdram-specific signal; low-true input. d-ras#, together with a[max:0 ], d-ba[1:0], d-cke, d-cs#, d-cas#, and d-we#, define the lpsdram command or operation. d-ras# is sampled on the rising edge of d-clk. 2 d-cas# input lpsdram column address strobe: lpsdram-specific signal; low-true input. d-cas#, together with a[max:0 ], d-ba[1:0], d-cke, d-cs#, d-ras#, and d-we#, define the lpsdram command or operation. d-cas# is sampled on the rising edge of d-clk. 2 d[2:1]-cs# input lpsdram chip select: lpsdram-specific signal; low-true input. when low, d-cs# selects the associated lpsdram memory die and starts the command input cycle. when d-cs# is high, commands are ignored but operations continue. ? d-cs#, together with a[max:0], d-ba[1:0], d-cke, d-ras#, d-cas#, and d-we#, define the lpsdram command or operation. d-cs# is sampled on the rising edge of d-clk. ? d[2:1]-cs# are dedicated to lpsdram die #2 and die #1, respectively, if present. otherwise, any unused lpsdram chip selects should be treated as rfu. 2 d-dm[1:0] input lpsdram data mask: lpsdram-specific signal; high-true input. when high, d-dm[1:0] controls masking of input data during writes and output data during reads. ? d-dm1 corresponds to the data on dq[15:8]. ? d-dm0 corresponds to the data on dq[7:0]. 2,3 table 3. signal descriptions for x16d / x16d ad-mux ballout (sheet 3 of 4) symbol type signal descriptions notes
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 22 order number: 309823, revision: 003 notes: 1. f4-ce# and a27 share the same package ball at location e6 . only one signal function is available, depending on the stacked device combination. 2. only available on stacked device combinations with na nd, sram, and/or lpsdram die; otherwise, treated as rfu. 3. d-dm[1:0] and s-ub#/s-lb# share the same package balls at locations h8 and h9, respectively. only one signal function for each ball location is available, depending on the stacked device combination. 4. s-cs1# and n-re# share the same package ball at location f6. only one signal function is available, depending on the stacked device combination. 5. s-cs2 and n-we# share the same package ball at location h2. only one signal function is available, depending on the stacked device combination. d-udqs d-ldqs input / output lpsdram upper/lower data strobe: ddr lpsdram-specific input/output signals. d-udqs and d-ldqs provide as output the read-dat a strobes, and as input the write-data strobes. ? d-udqs corresponds to the data on dq[15:8]. ? d-ldqs corresponds to the data on dq[7:0]. 2 s-cs1# s-cs2 input sram chip selects: sram-specific signals; s-cs1# low-true input, s-cs2 high-true input. when both are asserted, s-cs1# and s-cs2 select the sram die. when either is deasserted, the sram die is deselected and its power is reduced to standby levels. 2,5,6 s-ub# s-lb# input sram upper/lower byte enables: sram-specific signals; low-true inputs. when low, s-ub# enables dq[15:8] and s-lb# enables dq[7:0] during sram read and write cycles. when high, s-ub# masks dq[15:8] and s-lb# masks dq[7:0]. 2,3 power signals f-vpp power flash program/erase voltage: flash specific. f-vpp supplies program or erase power to the flash die. f-vcc power flash core power supply: flash specific. f-vcc supplies the core power to the flash die. vccq power i/o power supply: global device i/o power. vccq supplies the device input/output driver voltage. d-vcc power lpsdram core power supply: lpsdram specific. d-vcc supplies the core power to the lpsdram die. 2 s-vcc power sram power supply: sram specific. s-vcc supplies the core power to the sram die. 2 vss ground device ground: global ground reference for all signals and power supplies. connect all vss balls to system ground. do not float any vss connections. du ? do not use: this ball should not be connected to any power supplie s, signals, or other balls. this ball can be left floating. rfu ? reserved for future use: reserved by intel for future device functiona lity and enhancement. this ball must be left floating. table 3. signal descriptions for x16d / x16d ad-mux ballout (sheet 4 of 4) symbol type signal descriptions notes
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 23 4.3 signal ballouts x16c 4.3.1 x16c (107-ball) ballout, non-mux figure 9. x16c (107-ball) electrical ballout, non-mux pin 1 123456789 a du n-cle a27 a26 p-vcc f-dpd vss du a b du a4 a18 a19 vss f1-vcc f2-vcc a21 a11 b c n-ale a5 r-lb# a23 vss s-cs2 clk a22 a12 c d vss a3 a17 a24 f-vpp r-we# p1-cs# a9 a13 d e vss a2 a7 a25 f-wp1# adv# a20 a10 a15 e f f-wp2# a1 a6 r-ub# f-rst# f-we# a8 a14 a16 f g vccq a0 dq8 dq2 dq10 dq5 dq13 wait f2-ce# g h vss r-oe# dq0 dq1 dq3 dq12 dq14 dq7 f2-oe# / n-re# h j rfu s-cs1# / n-we# f1-oe# dq9 dq11 dq4 dq6 dq15 vccq j k f4-ce# f1-ce# p2-cs# f3-ce# s-vcc p-vcc f2-vcc vccq p-mode# / p-cre k l rfu vss vss vccq f1-vcc vss vss vss vss l m du n-ry/by# rfu rfu rfu rfu rfu rfu du m 123456789 legend: reserved for future use do not use top view - ball side down active balls
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 24 order number: 309823, revision: 003 4.3.2 x16c ad-mux (107-ball) ballout figure 10. x16c ad-mux (107-ball) electrical ballout pin 1 123456789 a du n-cle a27 a26 p-vcc f-dpd vss du a b du rfu a18 a19 vss f1-vcc f2-vcc a21 rfu b c n-ale rfu r-lb# a23 vss s-cs2 clk a22 rfu c d vss rfu a17 a24 f-vpp r-we# p1-cs# rfu rfu d e vss rfu rfu a25 f-wp1# adv# a20 rfu rfu e f f-wp2# rfu rfu r-ub# f-rst# f-we# rfu rfu a16 f g vccq rfu ad8 ad2 ad10 ad5 ad13 wait f2-ce# g h vss r-oe# ad0 ad1 ad3 ad12 ad14 ad7 f2-oe# / n-re# h jrfu s-cs1# / n-we# f1-oe#ad9ad11ad4 ad6ad15vccq j k f4-ce# f1-ce# p2-cs# f3-ce# s-vcc p-vcc f2-vcc vccq p-mode# / p-cre k l rfu vss vss vccq f1-vcc vss vss vss vss l m du n-ry/by# rfu rfu rfu rfu rfu rfu du m 123456789 top view - ball side down legend: active balls reserved for future use do not use
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 25 4.4 signal descriptions x16c table 4. signal descriptions for x16c / x16c ad-mux ballout (sheet 1 of 4) symbol type signal descriptions notes address and data signals, non-mux a[max:0] input address: global device signals. shared address inputs for all memory die during read and write operations. ? 4-gbit: amax = a27? 128-mbit: amax = a22 ? 2-gbit: amax = a26? 64-mbit: amax = a21 ? 1-gbit: amax = a25? 32-mbit: amax = a20 ? 512-mbit: amax = a24? 16-mbit: amax = a19 ? 256-mbit: amax = a23? 8-mbit: amax = a18 unused address inputs should be treated as rfu. dq[15:0] input / output data input/outputs: global device signals. inputs data and commands during write cycles, outputs data during read cycles. data signals are high-z when the device is deselected or its output is disabled. adv# input address valid: flash- and synchronous psram-specific signal; low-true input. during synchronous flash read operations, the addr ess is latched on the rising edge of f-adv#, or on the first rising edge of f-clk after f-adv# goes low for devices that support up to 108 mhz, or on the last rising edge of f-clk after f-adv# goes low for devices that support up to 133 mhz. in an asynchronous flash read operation, the addr ess is latched on the rising edge of adv# or continuously flows through while adv# is low. address and data signals, ad-mux a[max:16] input address: global device signals. shared address inputs for all memory die during read and write operations. ? 4-gbit: amax = a27? 128-mbit: amax = a22 ? 2-gbit: amax = a26? 64-mbit: amax = a21 ? 1-gbit: amax = a25? 32-mbit: amax = a20 ? 512-mbit: amax = a24? 16-mbit: amax = a19 ? 256-mbit: amax = a23? 8-mbit: amax = a18 unused address inputs should be treated as rfu. ad[15:0] input / output address-data multiplexed inputs/ outputs: global device signals. during ad-mux write cycles, ad[15:0] are used to input the lower address followed by commands or data. during ad-mux read cycles, ad[15:0] are used to input the lower address followed by read-data output. during nand accesses, ad[7:0] is used to input commands, address-data, or write-data, and output read-data. ad[15:0] are high-z when the device is deselected or its output is disabled. adv# input address valid: flash- and synchronous psram-specific signal; low-true input. during synchronous flash read operations, the addr ess is latched on the rising edge of f-adv#, or on the first rising edge of f-clk after f-adv# goes low for devices that support up to 108 mhz, or on the last rising edge of f-clk after f-adv# goes low for devices that support up to 133 mhz. in an asynchronous flash read operation, the address is latched on the rising edge of adv#. control signals
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 26 order number: 309823, revision: 003 f[4:1]-ce# input flash chip enable: flash-specific signal; low-true input. when low, f-ce# selects the associated flash memory die. when high, f-ce# deselects the associated flash die. flash die power is reduced to standby levels, and its data and f-wait outputs are placed in a high-z state. ? f1-ce# is dedicated to flash die #1. ? f[4:2]-ce# are dedicated to flash die #4 through #2, respectively, if present. otherwise, any unused flash chip enable should be treated as rfu. ? for nor/nand stacked device, f1-ce# selects nor die #1, f2-ce# selects nor die #2 while f4-ce# selects nand die #1 and nand die #2 using virtual chip-select scheme, f3-ce# selects nand die #3 if present. clk input clock: flash- and synchronous ps ram-specific input signal. clk synchronizes the flash and/or synchronous ps ram with the system clock during synchronous operations. f[2:1]-oe# input flash output enable: flash-specific signal; low-true input. when low, f-oe# enables the output drivers of t he selected flash die. when high, f-oe# disables the output drivers of the selected flash die and places the output drivers in high-z. ? for nor only stacked device, f[2:1]-oe# are common to all nor dies in the device. ? for nor/nand stacked device, f1-oe# enables all nor dies, f2-oe# selects all nand dies if present. 2 r-oe# input ram output enable: psram- and sram-specific signal; low-true input. when low, r-oe# enables the output drivers of the selected memory die. when high, r-oe# disables the output drivers of the selected memo ry die and places the output drivers in high-z. 1 f-rst# input flash reset: flash-specific signal; low-true input. when low, f-rst# resets internal operations a nd inhibits writes. when high, f-rst# enables normal operation. wait output wait: flash -and synchronous psram-specific signal; configurable true-level output. when asserted, wait indicates invalid output data. when deasserted, wait indicates valid output data. ? wait is driven whenever the flash or the synchronous psram is selected and its output enable is low. ? wait is high-z whenever flash or the synchronous psram is deselected, or its output enable is high. f-we# input flash write enable: flash-specific signal; low-true input. when low, f-we# enables write operations for the enabled flash die. address and data are latched on the rising edge of f-we#. r-we# input ram write enable: psram- and sram-specific signal; low-true input. when low, r-we# enables write operations for the selected memory die. data is latched on the rising edge of r-we#. 1 f-wp[2:1]# input flash write protect: flash-specific signals; low-true inputs. when low, f-wp# enables the lock-down mechanism. when high, f-wp# overrides the lock- down function, enabling locked-down blocks to be unlocked with the unlock command. ? f-wp1# is dedicated to flash die #1. ? f-wp2# is common to all other flash dies, if present. otherwise it is rfu. ? for nor/nand stacked device, f-wp1# selects all nor dies, while f-wp2# selects all nand dies. f-dpd input flash deep power-down: flash-specific signal; configurable-true input. when enabled in the ecr, f-dpd is used to enter and exit deep power-down mode. n-cle input nand command latch enable: nand-specific signal; high-true input. when high, n-cle enables commands to be latched on the rising edge of n-we#. 1 table 4. signal descriptions for x16c / x16c ad-mux ballout (sheet 2 of 4) symbol type signal descriptions notes
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 27 n-ale input nand address latch enable: nand-specific signal; high-true input. when high, n-ale enables addresses to be latched on the rising edge of n-we#. 1 n-re# input nand read enable: nand-specific signal; low-true input. when low, n-re# enables the output drivers of the selected nand die. when high, n-re# disables the output drivers of the selected nand die and places the output drivers in high-z. 1,2 n-ry/by# output nand ready/busy: nand-specific signal; low-true output. when low, n-ry/by# indicates the nand is busy performing a read, program, or erase operation. when high, n-ry/by# indicates the nand device is ready. 1 n-we# input nand write enable: nand-specific signal; low-true input. when low, n-we# enables write operations for the enabled nand die. 1,4 p-cre input psram control register enable: synchronous psram-specific signal; high-true input. when high, p-cre enables access to the refresh control register (p-rcr) or bus control register (p-bcr). when low, p-cre enables normal read or write operations. 1,3 p-mode# input psram mode#: asynchronous only psram-specific signal; low-true input. when low, p-mode# enables access to the configuration register, and to enter or exit low-power mode. when high, p-mode# enables normal read or write operations. 1,3 p[2:1]-cs# input psram chip select: psram-specific signal; low-true input. when low, p-cs# selects the associated psram memory die. when high, p-cs# deselects the associated psram die. psram die power is reduced to standby levels, and its data and wait outputs are placed in a high-z state. ? p1-cs# is dedicated to psram die #1. ? p2-cs# is dedicated to psram die #2. otherwise, any unused psram chip select should be treated as rfu. 1 s-cs1# s-cs2 input sram chip selects: sram-specific signals; s-cs1# low-true input, s-cs2 high-true input. when both s-cs1# and s-cs2 are asserted, the sram die is selected. when either s-cs1# or s-cs2 is deasserted, the sram die is deselected. 1,4 r-ub# r-lb# input ram upper/lower byte enables: psram- and sram-specific signals; low-true inputs. when low, r-ub# enables dq[15:8] and r-lb# enables dq[7:0] during psram or sram read and write cycles. when high, r-ub# masks dq[15:8] and r-lb# masks dq[7:0]. 1 power signals f-vpp power flash program/erase voltage: flash specific. f-vpp supplies program or erase power to the flash die. f[2:1]-vcc power flash core power supply: flash specific. f[2:1]-vcc supplies the core power to the flash die. ? for nor/nand stacked device, f1-vcc is dedicated for all nor dies, f2-vcc is dedicated for all nand dies. vccq power i/o power supply: global device i/o power. vccq supplies the device input/output driver voltage. p-vcc power psram core power supply: psram specific. p-vcc supplies the core power to the psram die. 1 s-vcc power sram power supply: sram specific. s-vcc supplies the core power to the sram die. 1 table 4. signal descriptions for x16c / x16c ad-mux ballout (sheet 3 of 4) symbol type signal descriptions notes
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 28 order number: 309823, revision: 003 notes: 1. only available on stacked device combinations with nand, sram, and/or lpsdram die. otherwise treated as rfu. 2. f2-oe# and n-re# share the same package ball at location h9. only one signal function is available, depending on the stacked device combination. 3. p-cre and p-mode# share the same package ball at location k9. only one signal function is available, depending on the stacked device combination. 4. s-cs1# and n-we# share the same package ball at location j2. only one signal function is available, depending on the stacked device combination. vss ground device ground: global ground reference for all signals and power supplies. connect all vss balls to system ground. do not float any vss connections. du ? do not use: this ball should not be connected to any power s upplies, signals, or other balls. this ball can be left floating. rfu ? reserved for future use: reserved by intel for future device functiona lity and enhancement. this ball must be left floating. table 4. signal descriptions for x16c / x16c ad-mux ballout (sheet 4 of 4) symbol type signal descriptions notes
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 29 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. notice: this document contains information available at the time of its release. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design . table 5. absolute maximum ratings parameter min max unit conditions notes temperature under bias expanded ?30 +85 c ? ? storage temperature ?65 +125 c ? ? f-vcc voltage ?2.0 v ccq (max) + 2.0 v ? 1,2 vccq ?2.0 v ccq (max) + 2.0 v ? 1,3 voltage on any input/output signal (except vcc, vccq, and vpp) ?2.0 v ccq (max) + 2.0 v ? 1,3 f-vpp voltage ?2.0 +11.5 v ? 1,3 i sh output short circuit current ? 100 ma ? 4 v pph time ? 80 hours 5 block program/erase cycles: main and efa blocks 100,000 ? cycles f-vpp = v cc or f-vpp = v pph 5 notes: 1. voltage is referenced to v ss . 2. during signal transitions, minimum dc voltage may undershoot to ?2.0 v for periods < 20 ns; maximum dc voltage may overshoot to v cc (max) + 2.0 v for periods < 20 ns. 3. during signal transitions, minimum dc voltage may undershoot to ?1.0 v for periods < 20 ns; maximum dc voltage may overshoot to v ccq (max) + 1.0 v for periods < 20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 5. operation beyond this limit may degrade performance.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 30 order number: 309823, revision: 003 5.2 operating conditions warning: operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 6. operating conditions symbol description min max unit conditions t c operating temperature (case temperature) ?30 +85 c ? v cc vcc supply voltage +1.7 +2.0 v ? v ccq i/o supply voltage +1.7 +2.0 v ? v ppl programming voltage (logic level) +0.9 +2.0 v ? v pph factory programming voltage (high level) +8.5 +9.5 v ?
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 31 6.0 electrical characteristics 6.1 dc current specifications table 7. dc current specifications (sheet 1 of 2) sym parameter density 1.7 v ? 2.0 v unit test conditions notes typ max i li input load current ? 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or v ss 1 i lo output leakage current ? 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or v ss i ccs v cc standby 256-mb 512-mb 35 50 95 120 a v cc = v cc max v ccq = v ccq max ce# = v ccq rst# = v ccq or gnd (for i ccs ) wp# = v ih 1,2 i ccaps aps 256-mb 512-mb 35 50 95 120 a v cc = v cc max v ccq = v ccq max ce# = v ssq rst# = v ccq all inputs are at rail to rail (v ccq or v ssq ). ? i dpd dpd 256 mbit 512 mbit 230 a v cc = v cc max v ccq = v ccq max ce# = v ccq rst# = v ccq ecr[15] = v ccq dpd = v ccq or v ssq all inputs are at rail to rail (v ccq or v ssq ). 8 i ccr average v cc read: asynchronous single word read f = 5 mhz, (1 clk) ? 256 mbit 512 mbit 25 30 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5 i ccr average v cc read: page mode read f = 13 mhz, (17 clk) 16 word 256 mbit 512 mbit 11 15 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5 i ccr average v cc read: synchronous burst read f = 66 mhz, lc = 7 burst = 8 word 256 mbit 512 mbit 22 32 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5 burst = 16 word 256 mbit 512 mbit 19 26 ma continuous 256 mbit 512 mbit 25 34 ma
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 32 order number: 309823, revision: 003 i ccr average v cc read: synchronous burst read f = 108 mhz, lc = 10 burst = 8 word 256 mbit 512 mbit 26 36 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5 burst = 16 word 256 mbit 512 mbit 23 30 ma continuous 256 mbit 512 mbit 30 42 ma i ccr average v cc read: synchronous burst read f = 133 mhz, lc = 13 burst = 8 word 256 mbit 512 mbit 26 35 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5 burst = 16 word 256 mbit 512 mbit 24 33 ma continuous 256 mbit 512 mbit 33 46 ma i ccw, i cce i ccbc v cc program v cc erase v cc blank check 35 50 ma v pp = v ppl or v pp = v pph , program/erase in progress 1,3,4, 5,7 i ccws, i cces v cc program suspend v cc erase suspend 256-mb 512-mb 35 50 95 120 a ce# = v ccq ; suspend in progress 1,3,6 i pps, i ppws, i ppes v pp standby v pp program suspend v pp erase suspend 0.2 5 a v pp = v ppl; suspend in progress 3 i ppr v pp read 2 15 av pp v cc 3 i ppw v pp program 0.05 0.1 ma v pp = v ppl = v pph, program in progress 3 i ppe v pp erase 0.05 0.1 ma v pp = v ppl = v pph, erase in progress 3 i ppbc v pp blank check 0.05 0.1 ma v pp = v ppl = v pph, blank check in progress 3 notes: 1. all currents are rms unless noted. typical values at typical v cc , t c = +25c. 2. i ccs is the average current measured over any 5 ms time interval 5 s after ce# is deasserted. 3. sampled, not 100% tested. 4. v cc read + program current is the sum of v cc read and v cc program currents. 5. v cc read + erase current is the sum of v cc read and v cc erase currents. 6. i cces is specified with the device deselected. if device is read while in erase suspend, current is i cces plus i ccr 7. i ccw , i cce measured over typical or max times specified in section 7.4, ?program and erase characteristics? on page 59 8. i dpd is the current measured 40 s after entering dpd state by asserting dpd. table 7. dc current specifications (sheet 2 of 2) sym parameter density 1.7 v ? 2.0 v unit test conditions notes typ max
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 33 6.2 dc voltage specifications 6.3 capacitance table 8. dc voltage specifications sym parameter v ccq 1.7 v ? 2.0 v unit test condition notes min max v il input low voltage 0 0.4 v ?1 v ih input high voltage v ccq ?0.4 v ccq ?? v ol output low voltage ? 0.1 v cc = v cc min v ccq = v ccq min i ol = 100 a ? v oh output high voltage v ccq ?0.1 ? v cc = v cc min v ccq = v ccq min i oh = ?100 a ? v pplk v pp lock-out voltage ? 0.4 ? 2 v lko v cc lock voltage 1.0 ? ? ? v lkoq v ccq lock voltage 0.9 ? ? ? notes: 1. during signal transitions, voltage can undershoot to ?1.0 v and overshoot to maximum v ccq +1.0v for durations of <2 ns. 2. v pp v pplk inhibits erase and program operations. do not use v ppl and v pph outside their valid ranges. table 9. capacitance symbol parameter min typ max unit condition note c in input capacitance (address, clk, ce#, oe#, adv#, we#, wp#, dpd and rst#) 246 pf v in = 0.0 - 2.0 v 1,2 c out output capacitance (data and wait) 256 v out = 0.0 - 2.0 v notes: 1. t c = +25c, f = 1 mhz. 2. sampled, not 100% tested.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 34 order number: 309823, revision: 003 7.0 nor flash ac characteristics timing symbols used in the timing diagrams within this document conform to the following convention: note: exceptions to this convention include tacc and tapa. tacc is a generic timing symbol that refers to the aggregate initial-access delay as determined by tavqv, telqv, and tglqv (whichever is satisfied last) of the flash device. tapa is specified in the flash device?s data sheet, and is the address-to-data delay for subsequent page-mode reads. signal code state code address a high h data - read q low l data - write d high-z z chip enable (ce#) e low-z x output enable (oe#) g valid v write enable (we#) w invalid i address valid (adv#) v reset (rst#) p clock (clk) c wait t e t l q v source signal target state source state target signal
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 35 7.1 ac test conditions note: ac test inputs are driven at v ccq for logic ?1? and 0.0 v for logic ?0 ?. input/output timing begins/ends at v ccq /2. notes: 1. see the following table for component values. 2. test configuration component value for worst case speed conditions. 3. c l includes jig capacitance. figure 11. ac input/output reference waveform v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input output v ih v il t rise/f al l table 10. ac input requirements symbol parameter frequency min max unit condition t rise/ fall inputs rise/fall time (address, clk, ce#, oe#, adv#, we#, wp#) 133mhz, 108mhz 0.3 1.2 ns v il to v ih or v ih to v il @66mhz 0 3 t askw address-address skew 0 3 at v ccq /2 figure 12. transient equivalent testing load circuit device under test out c l table 11. test configuration component value for worst case speed conditions test configuration c l (pf) 1.7 v standard test 30 2.0 v standard test 30
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 36 order number: 309823, revision: 003 7.2 read specifications the m18 device includes read specifications for the following speeds and voltage levels: ? 512-mbit device: 108 mhz, v ccq = 1.7 v to 2.0 v ? 256-mbit device: 133 mhz, v ccq = 1.7 v to 2.0 v devices which support frequencies up to 133 mhz must meet additional timing specifications for synchronous reads (for address latching with clk) as listed in table 13 . figure 13. clock input ac waveform clk [c] v ih v il r203 r202 r201 table 12. ac read, 512 mbit, 108 mhz, v ccq = 1.7 v to 2.0 v (sheet 1 of 2) nbr. symbol parameter 1 ?96 units notes min max asynchronous specifications r1 t avav read cycle time 96 ? ns ? r2 t avqv address to output valid ? 96 ns ? r3 t elqv ce# low to output valid ? 96 ns ? r4 t glqv oe# low to output valid ? 20 ns 2 r5 t phqv rst# high to output valid ? 150 ns ? r6 t elqx ce# low to output in low-z 0 ? ns 3 r7 t glqx oe# low to output in low-z 0 ? ns 2,3 r8 t ehqz ce# high to output in high-z ? 9 ns 3 r9 t ghqz oe# high to output in high-z ? 9 ns r10 t oh output hold from first occurring address, ce#, or oe# change 0 ? ns r11 t ehel ce# pulse width high 9 ? ns ? r12 t eltv ce# low to wait valid ? 11 ns ? r13 t ehtz ce# high to wait high z ? 9 ns 3 r14 t ghtv oe# high to wait valid (ad-mux only) ? 7 ns ?
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 37 r15 t gltv oe# low to wait valid ? 7 ns ? r16 t gltx oe# low to wait in low-z 0 ? ns 3 r17 t ghtz oe# low to wait in high-z (non-mux only) 0 9 ns 3 latching specifications r101 t avvh address setup to adv# high 5 ? ns ? r102 t elvh ce# low to adv# high 9 ? ns r103 t vlqv adv# low to output valid 96 ns r104 t vlvh adv# pulse width low 7 ? ns r105 t vhvl adv# pulse width high 7 ? ns r106 t vhax address hold from adv# high 5 ? ns 4 r107 t vhgl adv# high to oe# low (ad-mux only) 7 ? ns ? r108 t apa page address access (non-mux only) ? 15 ns r111 t phvh rst# high to adv# high 30 ? ns clock specifications r200 f clk clk frequency ? 108 mhz ? r201 t clk clk period 9.26 ? ns r202 t ch/cl clk high/low time 3.5 ? ns r203 t fclk/ rclk clk fall/rise time 0.3 1.2 ns synchronous specifications r301 t avch address setup to clk high 5 ? ns ? r302 t vlch adv# low setup to clk high 5 ? ns r303 t elch ce# low setup to clk high 5 ? ns r304 t chqv clk to output valid ? 7 ns r305 t chqx output hold from clk high 2 ? ns ? r306 t chax address hold from clk high 5 ? ns 4 r307 t chtv clk high to wait valid ? 7 ns ? r311 t chvl clk high to adv# setup 0 ? ns ? r312 t chtx wait hold from clk 2 ? ns ? notes: 1. see figure 11, ?ac input/output reference waveform? on page 35 for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv. 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax , whichever timing specification is satisfied first. table 12. ac read, 512 mbit, 108 mhz, v ccq = 1.7 v to 2.0 v (sheet 2 of 2) nbr. symbol parameter 1 ?96 units notes min max
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 38 order number: 309823, revision: 003 table 13. ac read, 256 mbit, 133 mhz, v ccq = 1.7 v to 2.0 v (sheet 1 of 2) nbr. symbol parameter 1 ?96 units notes min max asynchronous specifications r1 t avav read cycle time 96 ? ns ? r2 t avqv address to output valid ? 96 ns ? r3 t elqv ce# low to output valid ? 96 ns ? r4 t glqv oe# low to output valid ? 7 ns 2 r5 t phqv rst# high to output valid ? 150 ns ? r6 t elqx ce# low to output in low-z 0 ? ns 3 r7 t glqx oe# low to output in low-z 0 ? ns 2,3 r8 t ehqz ce# high to output in high-z ? 7 ns 3 r9 t ghqz oe# high to output in high-z ? 7 ns r10 t oh output hold from first occurring address, ce#, or oe# change 0 ? ns r11 t ehel ce# pulse width high 7 ? ns ? r12 t eltv ce# low to wait valid ? 8 ns ? r13 t ehtz ce# high to wait high z ? 7 ns 3 r14 t ghtv oe# high to wait valid (ad-mux only) ? 5.5 ns ? r15 t gltv oe# low to wait valid ? 5.5 ns ? r16 t gltx oe# low to wait in low-z 0 ? ns 3 r17 t ghtz oe# high to wait in high-z (non-mux only) 0 7 ns 3 latching specifications r101 t avvh address setup to adv# high 5 ? ns ? r102 t elvh ce# low to adv# high 7 ? ns r103 t vlqv adv# low to output valid 96 ns r104 t vlvh adv# pulse width low 7 ? ns r105 t vhvl adv# pulse width high 7 ? ns r106 t vhax address hold from adv# high 5 ? ns r107 t vhgl adv# high to oe# low (ad-mux only) 2 ? ns r108 t apa page address access (non-mux only) ? 15 ns r111 t phvh rst# high to adv# high 30 ? ns clock specifications r200 f clk clk frequency ? 133 mhz ? r201 t clk clk period 7.5 ? ns r202 t ch/cl clk high/low time 3.2 ? ns r203 t fclk/ rclk clk fall/rise time 0.3 1.2 ns synchronous specifications
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 39 r301 t avch address setup to clk high 2 ? ns ? r302 t vlch adv# low setup to clk high 2 ? ns r303 t elch ce# low setup to clk high 2.5 ? ns r304 t chqv clk to output valid ? 5.5 ns r305 t chqx output hold from clk high 2 ? ns r306 t chax address hold from clk high 2 ? ns r307 t chtv clk high to wait valid ? 5.5 ns r311 t chvl clk high to adv# setup 0 ? ns r312 t chtx wait hold from clk high 2 ? ns r313 t chvh adv# hold from clk high 2 ? ns r314 t chgl clk to oe# low (ad-mux only) 2 ? ns r315 t acc read access time from address latching clock 96 ? ns r316 t vlvh adv# pulse width low for sync reads 1 2 clks r317 t vhch adv# high to clk high 2 ? ns notes: 1. see figure 11, ?ac input/output reference waveform? on page 35 for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv. 3. sampled, not 100% tested. table 13. ac read, 256 mbit, 133 mhz, v ccq = 1.7 v to 2.0 v (sheet 2 of 2) nbr. symbol parameter 1 ?96 units notes min max
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 40 order number: 309823, revision: 003 7.2.1 timings: non mux device, asynchronous read note: wait polarity in figure is low-true (rcr10 = 0, default). wait deasserted during asynchronous reads. note: wait polarity in figure is low-true (rcr10 = 0, default). wait deasserted during asynchronous reads. figure 14. asynchronous single-word read with adv# latch r10 r7 r6 r17 r15 r9 r4 r8 r3 r106 r101 r105 r105 r2 r1 address [max:4] [a] a[3:0] adv#[v] ce# [e} oe# [g ] wait [t] data [d/q] figure 15. asynchronous page-mode read timing q0 q1 q14 q15 r108 r9 r7 r17 r15 r10 r4 r8 r3 r106 r101 r105 r105 r1 r1 r2 a ddress[max:4] [a] a[3:0] adv#[v] ce# [e] oe# [g] wait [t] dat a [d/q]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 41 7.2.2 timings: non mux device, synchronous read 108 mhz, 512 mb / notes: 1. wait polarity in figure is low-true (rcr10 = 0, default) 2. this figure illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by oe# and ce# deassertion after the first word in the burst. 3. address latched on rising clk edge after adv# low. notes: 1. at the end of word line (eowl); the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 16-word boundary aligned. 2. wait polarity in figure is low-true (rcr10 = 0, default) 3. address latched on rising clk edge after adv# low. figure 16. synchronous single-word array or non-array read 108 mhz, 512 mbit latency count r9 r8 r305 r304 r4 r13 r307 r16 r7 r303 r102 r3 r104 r106 r101 r104 r105 r105 r2 r306 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q] figure 17. continuous burst read, showing an output delay at eowl 108 mhz, 512 mbit r305 r305 r305 r305 r304 r4 r7 r312 r307 r15 r303 r102 r3 r106 r105 r105 r101 r2 r304 r304 r304 r306 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 42 order number: 309823, revision: 003 . notes: 1. wait polarity in figure is low-true (rcr10 = 0, default). 2. 8-word and 16-word burst are always wrap-only. 3. address latched on rising clk edge after adv# low. 7.2.3 timings: non mux device, synchronous read 133 mhz, 256 mb notes: 1. address is latched on first clk edge after adv# assertion, associated setup and hold timings shown. 2. wait polarity in figure is low-true (rcr10 = 0, default). figure 18. synchronous burst-mode unaligned eight-word burst read 108 mhz, 512 mbit a q 3 q 4 q 5 q 6 q 7 q 0 q1 q2 r1 7 r30 7 r305 r30 4 r4 r7 r307 r15 r303 r3 r106 r10 2 r105 r105 r101 r2 r306 r302 r301 clk [ c] a ddress [a] adv# [ v] ce# [ e] oe# [g] w ai t [ t] data [d/q] figure 19. synchronous array or non-array read 133 mhz, 256 mb clkn clk1 addr latched clk0 r311 r304 r305 r304 r305 r315 r304 r307 r15 r316 r317 r313 r316 r303 r306 r301 r302 clk [c] a ddr ess [a] ce# [e] adv# [v] oe# [g] wait [t] data [d/q]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 43 . notes: 1. address is latched on the second rising clk edge after adv# assertion, associated setup and hold timing shown. 2. wait polarity in figure is low-true (rcr10 = 0, default). notes: 1. at the end of word line (eowl); the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 16-word boundary aligned. 2. wait polarity in figure is low-true (rcr10 = 0, default). 3. address is latched on the first rising clk edge after adv# assertion, associated setup and hold timing shown. figure 20. synchronous array or non-array read with adv# maximum low pulse width 133 mhz, 256 mb clkn clk1 addr latched clk0 r304 r305 r315 r304 r307 r15 r316 r313 r316 r311 r303 r306 r301 r317 r302 clk [c] a ddress [a] ce# [e] adv# [v] oe# [g] wait [t] data [d/q] figure 21. continuous burst read, showing output delay at eowl 133 mhz, 256 mb clkn clk1 addr latched c lk0 r311 r304 r305 r304 r305 r315 r304 r307 r15 r 316 r317 r313 r 316 r303 r306 r301 r 302 clk [c] a ddr ess [a] ce# [e] adv# [v] oe# [g] wait [t] data [d/q]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 44 order number: 309823, revision: 003 . notes: 1. wait polarity in figure is low-true (rcr10 = 0, default). 2. 8-word and 16-word burst reads are always wrapped. 3. address is latched on the second rising clk edge after adv# assertion, associated setup and hold timing shown. figure 22. synchronous burst-mode unaligned eight-word burst read 133 mhz, 256 mb q2 q3 q4 q5 q6 q7 q0 q1 clkn clk1 addr latched clk0 r9 r8 r13 r304 r305 r315 r304 r307 r15 r316 r313 r316 r311 r303 r306 r301 r317 r302 clk [c] a ddress [a] ce# [e] adv# [v] oe# [g] wait [t] data [d/q]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 45 7.2.4 timings: ad-mux device, asynchronous read note: wait polarity in figure is low-true (rcr10 = 0, default). wait is deasserted during asynchronous reads. 7.2.5 timings: ad-mux device, synchronous read 108 mhz, 512 mb notes: 1. wait polarity in figure is low-true (rcr10 = 0, default).. 2. this figure illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by oe# and ce# deassertion after the first word in the burst. 3. address latched on first clk edge after adv# low. figure 23. asynchronous word read a q r4 r13 r12 r9 r7 r107 r8 r101 r106 r3 r2 a[m ax:16] a /d q[15:0] adv# [v] ce# [e] oe# [g] wait [t] figure 24. synchronous single-word array or non-array read 108 mhz, 512 mbit latency count a a q r13 r15 r12 r9 r107 r4 r8 r102 r303 r106 r105 r302 r105 r305 r304 r3 r101 r2 r301 r306 clk [c] a[max:16] a /dq[15:0] adv# [v] ce# [e] oe# [g] wait [t]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 46 order number: 309823, revision: 003 notes: 1. at the end of word line (eowl); the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 16-word boundary aligned. 2. wait polarity in figure is low-true (rcr10 = 0, default). 3. address latched on first clk edge after adv# low. . notes: 1. wait polarity in figure is low-true (rcr10 = 0, default). 2. address latched on first clk edge after adv# low. figure 25. continuous burst read, showing an output delay at eowl 108 mhz, 512 mbit fir st access latency a q q q q q r 307 r307 r 307 r15 r12 r 107 r4 r 102 r 303 r 302 r305 r304 r305 r 304 r3 r 301 clk [c] a[max:16] a /dq[15:0] adv# [v] ce# [e] oe# [g] wait [t] figure 26. synchronous burst-mode unaligned 16-word burst read 108 mhz, 512 mbit latency count a a q1 q1 q15 q0 r13 r14 r307 r307 r15 r12 r9 r 107 r4 r 102 r303 r302 r305 r304 r3 r301 clk [c] a[max:16] a /dq[15:0] adv# [v] ce# [e] oe# [g] wait [t]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 47 7.2.6 timings: ad-mux device, synchronous read 133 mhz, 256 mb notes: 1. address is latched on the first rising clk edge after adv# assertion, associated setup and hold timing shown. 2. wait polarity in figure is low-true (rcr10 = 0, default). . notes: 1. address is latched on the second rising clk edge after adv# assertion, associated setup and hold timing shown. 2. wait polarity in figure is low-true (rcr10 = 0, default). 3. 8-word and 16-word burst reads are always wrapped. figure 27. synchronous array or non-array read 133 mhz, 256 mb clkn clk1 addr latched clk0 r311 r307 r15 r12 r107 r316 r317 r313 r316 r303 r305 r304 r306 r301 r302 clk [c] a [max:16] [a] a/d q[15:0] ce# [e] adv# [v] oe# [g] wait [t] figure 28. synchronous unaligned eight-word burst read with adv# maximum low pulse width 133 mhz, 256 mb q2 q7 q0 q1 clkn clk1 addr latched clk0 r307 r 307 r15 r12 r9 r4 r314 r316 r313 r316 r311 r8 r303 r 304 r306 r 301 r317 r 302 clk [c] a [max:16] [a] a/d q [15:0] ce# [e] ad v# [v] oe# [g] wait [t]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 48 order number: 309823, revision: 003 notes: 1. at the end of word line (eowl); the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 16-word boundary aligned 2. wait polarity in figure is low-true (rcr10 = 0, default). 3. address is latched on the first rising clk edge after adv# assertion, associated setup and hold timing shown. figure 29. continuous burst read, showing an output delay at eowl 133 mhz, 256 mb clkn clk1 addr latched clk0 r311 r307 r307 r15 r12 r107 r 316 r 317 r313 r 316 r303 r305 r304 r306 r 301 r302 clk [c] a [max:16] [a] a/d q[15:0] ce# [e] adv# [v] oe# [g] wait [t]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 49 7.3 write specifications table 14. ac write specifications nbr. symbol parameter (1, 2) min max units notes w1 t phwl rst# high recovery to we# low 150 ? ns 1,2,3 w2 t elwl ce# setup to we# low 0 ? ns 1,2 w3 t wlwh we# write pulse width low 40 ? ns 1,2,4 w4 t dvwh data setup to we# high 40 ? ns 1,2 w5 t avw h address setup to we# high 40 ? ns w6 t wheh ce# hold from we# high 0 ? ns w7 t whdx data hold from we# high 0 ? ns w8 t whax address hold from we# high (non-mux only) 0 ? ns w9 t whwl we# pulse width high 20 ? ns 1,2,5 w10 t vpwh vpp setup to we# high 200 ? ns 1,2,3,7 w11 t qvvl vpp hold from status read 0 ? ns w12 t qvbl wp# hold from status read 0 ? ns w13 t bhwh wp# setup to we# high 200 ? ns w14 t whgl we# high to oe# low 0 ? ns 1,2,8 w15 t vlwh adv# low to we# high (ad-mux only) 55 ? ns 1,2 w16 t whqv we# high to read valid t avq v +30 ? ns 1,2,3,9 write to synchronous read specifications w19 t whch we# high to clock high 15 ? ns 1,2,3,6 bus write with active clock specifications w21 t vhwl adv# high to we# low ? 27 ns 1,2,10,11 w22 t chwl clock high to we# low ? 27 ns notes: 1. write timing characteristics during erase suspend are the same as write-only operations. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occu rs first). hence, t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl or t ehel ) is defined from ce# or we# high (whichever occurs first) to ce# or we# low (whichever occurs last). hence, t whwl = t ehel = t whel = t ehwl ). 6. t whch must be met when transitioning from a write cycle to a synchronous burst read. in addition there must be a ce# toggle after we# goes high. 7. vpp and wp# should be at a valid level until erase or program success is determined. 8. when doing a read status operation following any command that alters the status register data, w14 is 20ns. 9. add 10ns if the write operations results in a rcr or bl ock lock status change, for the subsequent read operation to reflect this change. 10. this specification is applicable only if the part is configured in synchronous mode and an active clock is running. either t vhwl or t chwl must be met depending on the whether the address is latched on adv# or clk. 11. these specifications are not applicable to 133 mhz devices.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 50 order number: 309823, revision: 003 7.3.1 timings: non mux device, asynchronous write note: wait polarity in figure is low-true (rcr10 = 0, default). wait deasserted during asynchronous reads and high-z during writes. figure 30. write to write figure 31. asynchronous read to write w13 w1 w7 w4 w7 w4 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w8 w8 w5 w5 a ddress [a] ad v# ce# [e} we# [w] oe# [g] data [d/q] rst# [p] wp# q d r5 w7 w4 r10 r7 r6 r17 r15 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 a ddress [a] ce# [e] oe# [g] we# [w] wait [t] data [d/q] rst# [p]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 51 figure 32. write to asynchronous read d q w1 r9 r8 r4 r3 r2 w7 w4 r17 r15 w1 4 w3 w3 r10 r11 r11 w6 w2 r1 r1 w8 w5 a ddress [a] ad v# [v] ce# [e} we# [w] oe# [g] wait [t] data [d/q] rst# [p]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 52 order number: 309823, revision: 003 7.3.2 timings: non mux device, synchronous write 108 mhz, 512 mb notes: 1. wait polarity in figure is low-true (rcr10 = 0, default). wait is high-z during write operations. 2. clock is ignored during write operation. figure 33. synchronous read to write 108 mhz, 512 mbit latency count q d d w7 r8 r305 r304 r7 r13 r307 r16 w1 5 w9 w19 w8 w9 w3 w22 w21 w3 w2 r9 r4 w6 r11 r11 r303 r3 w2 0 r104 r104 r106 r102 r105 r105 w1 8 w5 r101 r2 r306 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] we # wait [t] data [d/q]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 53 note: wait polarity in figure is low-true (rcr10 = 0, default). figure 34. write to synchronous read 108 mhz, 512 mbit d q q w1 r304 r305 r304 r3 w7 w4 r307 r1 5 r4 w16 w1 9 w3 w3 r1 1 r303 r1 1 w6 w2 r104 r106 r104 r306 w8 w5 r302 r301 r2 clk a ddress [a] adv# ce# [e} we # [w] oe# [g] wait [t] data [d/q] rst # [p]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 54 order number: 309823, revision: 003 7.3.3 timings: non mux device, synchronous write 133 mhz, 256 mb note: wait polarity in figure is lo w-true (rcr10 = 0, default). note: wait polarity in figure is lo w-true (rcr10 = 0, default). figure 35. synchronous read to write 133 mhz, 256 mb addr latched clk clkn clk1 addr latched clk0 r311 r311 r11 r304 r305 r315 r304 w21 r17 r13 r307 r15 r316 r317 r313 r316 r316 r317 r313 r316 r303 r306 r301 r302 r302 clk [c] a ddress [a] ce# [e] adv# [v] oe# [g] wait [t] we# data [d/q] figure 36. write to synchronous read 133 mhz, 256 mb d q address latched clk r305 r315 r304 w7 w4 r307 r15 w19 w3 w3 r11 r11 w6 w2 r316 r313 r302 r311 r306 r301 w8 w5 clk[c] a ddress [a] adv#[v] ce# [e] we# [w] oe# [g] wait [t] data [d/q]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 55 7.3.4 timings: ad-mux device, asynchronous write note: wait polarity in figure is low-true (rcr10 = 0, default). note: wait polarity in figure is low-true (rcr10 = 0, default). figure 37. write to write a d a d w1 3 w1 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w15 w8 w7 w4 w5 a[m a x- 1 6 ] [a] a /dq[15-0] [a/d] adv# [v] ce# [e] we# [w] oe# [g] rst# [p] wp# figure 38. asynchronous read to write a q a d r13 r12 r13 r12 w6 w4 w3 w3 w2 r9 r107 r8 r3 w7 w5 r10 r2 r1 r1 a[max:16] a /dq [15:0] ce# [e] adv#[v] oe# [g] we# [w] wait[t]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 56 order number: 309823, revision: 003 note: wait polarity in figure is lo w-true (rcr10 = 0, default). 7.3.5 timings: ad-mux device, synchronous write 108 mhz, 512 mb note: wait polarity in figure is lo w-true (rcr10 = 0, default). figure 39. write to asynchronous read a d a d a q w1 r13 r12 r13 r12 r9 r7 r4 w14 r107 w3 w9 w3 w18 w9 w3 w3 r8 r3 r11 r11 w6 w2 w2 w20 r2 w21 w15 w8 w7 w4 w5 a[max-16] a /dq[15-0] adv# [v] ce# [e] we# [w] oe# [g] wait [t] rst# [p] figure 40. synchronous read to write 108 mhz, 512 mbit a a q q a d a d r301 w15 w9 w7 w3 w9 w3 w2 r12 r13 r15 r12 r4 r11 r11 w20 w4 w5 r3 r7 r306 r2 clk [c] a[max:16] a /dq[15:0] adv# [v] ce# [e] oe# [g] wait [t] we# [w]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 57 note: wait polarity in figure is low-true (rcr10 = 0, default). 7.3.6 timings: ad-mux device, synchronous write 133 mhz, 256 mb note: wait polarity in figure is low-true (rcr10 = 0, default). figure 41. write to synchronous read 108 mhz, 512 mbit latency count d q q w1 r304 r305 r304 r3 w7 w4 r307 r12 r4 w1 9 w3 w3 r1 1 r303 r1 1 w6 w2 r104 r106 r104 r306 w8 w5 r302 r301 r2 clk a ddress [a] adv# ce# [e} we# [w] oe# [g] wai t [t ] data [d/q] rst # [p] figure 42. synchronous read to write 133 mhz, 256 mb q d clkn clk1 addr latched clk0 r14 r13 r15 r12 r107 w15 w3 w3 w21 r316 r317 r313 r311 r316 r303 w7 w8 r304 r305 r 304 w5 r306 r 301 r 302 clk a [max:16] [a] a/d q[15:0] ce# [e] adv# [v] we#[e] oe# [g] wait [t]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 58 order number: 309823, revision: 003 note: wait polarity in figure is lo w-true (rcr10 = 0, default). figure 43. write to synchronous read 133 mhz, 256 mb a d a q clkn clk1 addr latched clock r307 r15 r12 r13 r12 r4 r107 w27 w19 w5 w3 w21 w3 r303 w6 w2 r313 r316 r316 r311 r304 r305 r304 r301 w7 w4 r306 r317 r302 clk[c] a [max:16] [a] a/d q[15:0] adv# [v] ce# [e] we# [w] oe# [g] wait[t]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 59 7.4 program and erase characteristics table 15. program and erase characteristics nbr. symbol parameter v ppl /v pph units notes min typ max conventional word programming w200 t prog/w program time single word (first word) ? 115 230 s 1,2 single word (subsequent word) ? 50 230 single word (efa) ? 50 230 1 buffered programming w200 t prog/w program time single word ? 250 500 s 1 w250 t prog/pb one buffer (512 words) ? 2.15 4.3 ms buffered enhanced factory programming w451 t befp/w program single word ? 4.2 ? s 1,3,4 w452 t befp/setup buffered efp setup 5 ? ? 1 erasing and suspending w500 t ers/efa b erase time 4-kword efa block ? 0.4 2.5 s 1 w501 t ers/mab 128-kword main array block ? 0.9 4 w600 t susp/p suspend latency program suspend ? 20 25 s w601 t susp/e erase suspend ? 20 25 blank check w702 t bc/mb blank check main array block ? 3.2 ? ms 1 notes: 1. typical values measured at tc = +25 c and nominal volt ages. performance numbers are valid for all speed versions. sampled, but not 100% tested. 2. first and subsequent words refer to first word and subsequent words in control mode programming region. 3. averaged over entire device. 4. befp not validated at v ppl .
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 60 order number: 309823, revision: 003 7.5 reset specifications table 16. reset specifications nbr. symbol parameter min max unit notes p1 t plph rst# pulse width low 100 ns 1,2,3,4,7 p2 t plrh rst# low to device reset during erase 25 s 1,3,4,7 rst# low to device rese t during program 25 1,3,4,7 p3 t vccph v cc power valid to rst# de-assertion (high) 300 1,4,5,6 notes: 1. these specifications are valid for a ll device versions (packages and speeds). 2. the device may reset if t plph is < t plph min , but this is not guaranteed. 3. not applicable if rst# is tied to vccq. 4. sampled, but not 100% tested. 5. if rst# is tied to the v cc supply, device will not be ready until t vccph after v cc v cc min. 6. if rst# is tied to any supply/signal with v ccq voltage levels, the rst# input voltage must not exceed v cc until v cc v cc (min). 7. reset completes within t plph if rst# is asserted while no erase or program operation is executing. figure 44. reset operation timing ( a) reset during read mode (b) reset during program or block erase p1 p2 (c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v v cc (d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 61 7.6 deep power down specifications note: dpd pin is low-true (ecr14 = 0) note: dpd pin is low-true (ecr14 = 0) table 17. deep power down specifications nbr. symbol parameter min max unit notes s1 t slsh (t shsl ) dpd asserted pulse width 100 ns 1,2,3 s2 t ehsh (t ehsl ) ce# high to dpd asserted 0 s 1,2 s3 t shel (t slel ) dpd deasserted to ce# low 75 1,2 s4 t phel rst# high during dpd state to ce# low (dpd deasserted to ce# low) 75 1,2 notes: 1. these specifications are valid for al l device versions (packages and speeds). 2. sampled, but not 100% tested. 3. dpd must remain asserted for the duration of deep power down mode. dpd current levels are achieved 40 s after entering the dpd mode. figure 45. deep power down operation timing s3 s1 s2 dpd [s] ce# [e] rst# [p] figure 46. reset during deep power down operation timing s4 s2 rst# [p] dpd [s] ce# [e]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 62 order number: 309823, revision: 003 8.0 nor flash bus interface the flash device uses low-true control signal inputs, and is selected by asserting the chip enable (ce#) input. the output enable (oe#) input is asserted for read operations, while the write enable (we#) input is asserted for write operations. oe# and we# should never be asserted at the same time; otherwise, indeterminate device operation will result. all bus cycles to or from the flash memory conform to standard microcontroller bus cycles. commands are written to the device to control all operations. table 18 shows the logic levels that must be applied to the control-signal inputs of the device for the various bus operations. notes: 1. x = don?t care (high or low) 2. dpd polarity determined by ecr14. shown low-true here. 8.1 bus reads to perform a read operation, both ce# and oe# must be asserted; rst# and we# must be deasserted. oe# is the data-output control and when asserted, the output data is driven on to the data i/o bus. all read operations are independent of the voltage level on vpp. the automatic power savings (aps) feature provides low power operation following reads during active mode. after data is read from the memory array and the address lines are quiescent, aps automatically places the device into standby. in aps, device current is reduced to i ccaps . the device supports two read configurations: ? asynchronous reads. rcr15 = 1. this is the default configuration after power-up/reset. ? non-multiplexed devices support asynchronous page-mode reads. ad-multiplexed devices support only asychronous single-word reads. ? synchronous burst reads. rcr15 = 0. table 18. flash memory control signals operation rst# dpd 2 ce# 1 oe# 1 we# 1 address 1 data i/o reset low high x x x x high-z read high high low low high valid output output disable high high low high high x high-z write high high low high valid input high high high low valid input standby high high high x x x high-z deep power- down high low high x x x high-z
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 63 8.1.1 asynchronous single-word reads in asynchronous single-word read mode, a single word of data corresponding to the address is driven onto the data bus after the initial access delay. the address is latched when adv# is deasserted. for ad-multiplexed devices, adv# must be deasserted before oe# is asserted. if only asynchronous reads are to be performed, clk must be tied to a valid v ih level, and the wait signal can be floated. in addition, for non-multiplexed devices, adv# must be tied to ground. 8.1.2 asynchronous page mode (non-multiplexed devices only) in asynchronous page mode, sixteen data words are ?sensed? simultaneously from the flash memory array and loaded into an internal page buffer. the buffer word corresponding to the initial address is driven onto the data bus after the initial access delay. subsequent words in the page are output after the page access delay. a[3:0] bits determine which page word is output during a read operation. a[max:4] and adv# must be stable throughout the page access. wait is deasserted during asynchronous page mode. adv# can be driven high to latch the address, or held low throughout the read cycle. clk is not used for asynchronous page-mode reads, and is ignored. 8.1.3 synchronous burst mode synchronous burst mode is a clock-synchronous read operation that improves the read performance of flash memory over that of asynchronous reads. synchronous burst mode is enabled by programming the read configuration register (rcr) of the flash memory device. the rcr is also used to configure the burst parameters of the flash device, including latency count, burst length of 8, 16 and continuous, and wait polarity. three additional signals are used for burst mode: clk, adv#, and wait. the address for synchronous read operations is latched on the adv# rising edge or the first rising clk edge after adv# low, whichever occurs first for devices that support up to 108 mhz. for devices that support upto 133 mhz, the address is latched on the last clk edge when adv# is low. during synchronous read modes, the first word is output from the data buffer on the rising clk edge after the initial access latency delay. subsequent data is output on rising clk edges following a t chqv delay. however, for a synchronous non-array read, the same word of data will be output on successive rising clock edges until the burst length requirements are satisfied.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 64 order number: 309823, revision: 003 8.1.3.1 wait operation upon power up or exit from reset, wait polarity defaults to low-true operation (rcr10 = 0). during synchronous reads (rcr15 = 0), wait asserts when read data is invalid , and deasserts when read data is valid . during asynchronous reads (rcr15 = 1), wait is deasserted. during writes, wait is high-z on non-mux devices, and deasserted on ad-mux devices. table 19 summarizes wait behavior. notes: 1. x = don?t care (high or low). 2. active: wait asserted = invalid data; wait deasserted = valid data. 8.2 bus writes to perform a write operation, both ce# and we# are asserted while rst# and oe# are deasserted. all device write operations are asynchronous, with clk being ignored, but clk can be kept active/toggling. during a write operation, address and data are latched on the rising edge of we# or ce#, whichever occurs first. 8.3 reset the device enters a reset mode when rst# is asserted. in reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. the device shuts down any operation in progress, a process which takes a minimum amount of time to complete. to return from reset mode, rst# must be deasserted. normal operation is restored after a wake-up interval. 8.4 deep power-down the device enters dpd mode when the following two conditions are met: ecr15 is set(1) and dpd is asserted. the two conditions can be satisfied in any order. ecr14 bit determines the dpd asserted logic level. while in this mode, rst# and ce# must be deasserted. table 19. wait behavior summary device operation ce# oe# we# wait notes device not selected standby high x x high-z 1 non-mux device output disable low high high high-z sync read low high active 2 async read low high deasserted write high low high-z ad-mux device output disable high high deasserted sync read low high active 2 async read low high deasserted write high low deasserted
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 65 the device exits dpd mode when dpd is deasserted. there is an exit latency before the device returns to standby mode and any operations are allowed. see section 7.6, ?deep power down specifications? on page 61 for the timing specifications. the device should not be placed in dpd mode when a program/erase operation is ongoing or suspended. if the device enters dpd mode in the middle of a program, erase or suspend, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid. while in dpd mode, the read-mode of each partition, configuration registers (rcr and ecr), and block lock bits, are preserved. status register is reset to 0080h; i.e., if the status register contains error bits, they will be cleared. 8.5 standby when ce# is deasserted, the device is deselected and placed in standby, substantially reducing power consumption. in standby, data outputs are placed in high-z, independent of the level placed on oe#. if deselected during a program or erase operation, the device continues to consume active power until the operation is complete. there is no additional latency for subsequent read operations. 8.6 output disable when oe# is deasserted with ce# asserted, the device outputs are disabled. output pins are placed in a high-impedance state. wait is deasserted in ad-muxed devices and driven to high-z in non-multiplexed devices. 8.7 bus cycle interleaving when issuing commands to the device, a read operation can occur between the two writes cycles of a 2-cycle command. (see figure 47 and figure 48 ) however, a write operation cannot occur between the two write cycles of a 2-cycle command and will cause a command sequence error (see figure 49 ). figure 47. operating mode with correct command sequence example partition a partition a partition b 0x20 0xd0 0xff a ddress [a] we# [w] oe# [g] data [d/q]
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 66 order number: 309823, revision: 003 8.7.1 read operation during program buffer fill due to the large buffer size of m18 devices, the system interrupt latency may be impacted during the buffer fill phase of a buffered programming operation. please refer to the relevant application note listed in appendix f, ?additional information? to implement a software solution for your system. 8.8 read-to-write and write-to-read bus transitions consecutive read and write bus cycles must be properly separated from each other to avoid bus contention. these cycle separation specs are described in the sections below. 8.8.1 write to asynchronous read transition to transition from a bus write to an asynchronous read operation, either ce# or adv# must be toggled after we# goes high. 8.8.2 write to synchronous read transition to transition from a bus write to a synchronous read operation, either ce# or adv# must be toggled after we# goes high. in addition, w19 (t whch -we# high to clk high) must be met. figure 48. operating mode with correct command sequence example figure 49. operating mode with illegal command sequence example partition a partition b partition a 0x20 valid array data 0xd0 a d d re ss [ a ] we# [w] oe# [g] data [d/q] partition a partition b partition a partition a 0x20 0xff 0xd0 sr[7:0] a d d re ss [ a ] we# [w] oe# [g] data [d/q]
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 67 8.8.3 asynchronous/synchronous read to write transition to transition from a asynchronous/synchronous read to a write operation, either ce# or adv# must be toggled after oe# goes high. 8.8.4 bus write with active clock to perform a bus write when the device is in synchronous mode and the clock is active, w21 (t vhwl - adv# high to we# low) or w22 (t chwl -clock high to we# low) must be met.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 68 order number: 309823, revision: 003 9.0 nor flash operations this section describes the operational features of nor flash memory. operations are command- based?command codes are first issued to the device, and then the device performs the desired operation. all command codes are issued to the device using bus-write cycles (see chapter 8.0, ?nor flash bus interface? ). a complete list of available command codes can be found in appendix a, ?device command codes? . 9.1 initialization proper device initialization and operation is dependent on the power-up/down sequence, reset procedure, and adequate power-supply decoupling. the following sections describe each of these areas. 9.1.1 power-up/down characteristics to prevent conditions that could result in spurious program or erase operations, the power-up/ power-down sequence shown in table 20 is recommended. note that each power supply must reach its minimum voltage range before applying/removing the next supply voltage. * power supplies connected or sequenced together. device inputs must not be driven until all supply voltages reach their minimum range. rst# should be low during power transitions. note: if v ccq is below v lkoq , the device is reset. 9.1.2 reset characteristics during power-up and power-down, rst# should be asserted to prevent spurious program or erase operations. while rst# is low, device operations are disabled, all inputs (e.g., address, control) are ignored, and all outputs (e.g., data, wait) are placed in high-z. invalid bus conditions are effectively masked out. upon power-up, rst# can be deasserted after t vccph , allowing the device to exit from reset. upon exiting from reset, the device defaults to asynchronous read array mode, and the status register defaults to 0080h. array data is available after t phqv , or a bus-write cycle can begin after t phwl . if rst# is asserted during a program or erase operation, the operation will abort and array contents at that location will be invalid. table 20. power-up/down sequence power supply voltage power-upsequence power-down sequence v cc(min) 1st 1st 1st* sequencing not required* 3rd 2nd 2nd* sequencing not required* v ccq(min) 2nd 2nd* 2nd 1st* v pp(min) 3rd 2nd 1st 1st
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 69 for proper system initialization, connect rst# to the low-true reset signal that asserts whenever the processor is reset. this will ensure the flash device is in the expected read mode (i.e., read array) upon startup. 9.1.3 power supply decoupling high-speed flash memories require adequate power-supply decoupling to prevent external transient noise from affecting device operations, and to prevent internally-generated transient noise from affecting other devices in the system. ceramic .01 to 0.1 fd capacitors should be used between all vcc, vccq, vpp supply connections and system ground. these high-frequency, inherently low-inductance capacitors should be placed as close as possible to the device package, or on the opposite side of the printed circuit board close to the center of the device-package footprint. larger (4.7 fd to 33.0 fd) electrolytic or tantulum bulk capacitors should also be distributed as needed throughout the system to compensate for voltage sags caused by circuit-board trace inductance. transient current magnitudes depend on the capacitive and inductive loading on the device?s outputs. for best signal integrity and device performance, high-speed design rules should be used when designing the printed-circuit board. circuit-trace impedances should match output-driver impedance with adequate ground-return paths. this will help minimize signal reflections (overshoot/undershoot) and noise caused by high-speed signal edge rates. 9.2 status register the status register (sr) is a 16-bit, read-only register that indicates device and partition status, and operational errors. to read the status register, issue the read status register command. subsequent reads output status register information on ad/dq[9:0], and 00h on ad/dq[15:10]. sr status bits are set and cleared by the device. sr error bits are set by the device, and must be cleared using the clear status register command. upon power-up or exit from reset, the status register defaults to 0080h. table 21 shows status register bit definitions.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 70 order number: 309823, revision: 003 9.2.1 clearing the status register the status register (sr) contain status and error bits which are set by the device. sr status bits are cleared by the device, however sr error bits are cleared by issuing the clear status register command (see table 22 ). resetting the device also clears the status register. table 21. status register bit definitions status register (sr) default value = 0080h reserved region program status ready status erase suspend status erase error program error program/ erase voltage error program suspend status block- locked error partition status 15-10 9-8 7 6 5 4 3 2 1 0 bit name description 15-10 reserved reserved for future use; these bits will always be set to zero. 9-8 region program status sr9 sr8 0 0 = region program successful. 1 0 = region program error - attempted write with object data to control mode region. 0 1 = region program error - attempted rewrite to object mode region. 1 1 = region program error - attempted write using illegal command. sr4 will also be set along with sr[8,9] for the above error conditions. 7 ready status 0 = device is busy; sr[9:8], sr[6:1] are invalid; 1 = device is ready; sr[9:8], sr[6:1] are valid. 6 erase suspend status 0 = erase suspend not in effect. 1 = erase suspend in effect. 5 erase error / blank check error command sequence error sr5 sr4 0 0 = program or erase operation successful. 0 1 = program error - operation aborted. 1 0 = erase error - operation aborted / blank check error - operation failed. 1 1 = command sequence error - command aborted. 4 program error 3v pp error 0 = v pp within acceptable limits during program or erase operation. 1 = v pp not within acceptable limits during program or erase operation. 2 program suspend status 0 = program suspend not in effect. 1 = program suspend in effect. 1 block-locked error 0 = block not locked during program or erase - operation successful. 1 = block locked during program or erase - operation aborted. 0 partition status sr7 sr0 0 0 = active program or erase operation in addressed partition. befp: program or verify complete, or ready for data. 0 1 = active program or erase operation in other partition. befp: program or verify in progress. 1 0 = no active program or erase operation in any partition. befp: operation complete 1 1 = reserved.
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 71 issuing the clear status register command places the addressed partition in read status register mode. other partitions are not affected. note: care should be taken to avoid status register ambiguity. if a command sequence error occurs while in an erase suspend condition, the status register will indicate a command sequence error by setting sr4 and sr5. when the erase operation is resumed (and finishes), any errors that may have occurred during the erase operation will be masked by the command sequence error. to avoid this situation, clear the status register prior to resuming a suspended erase operation. the clear status register command functions independent of the voltage level on vpp. 9.3 read configuration register the read configuration register (rcr) is a 16-bit read/write register used to select bus-read modes, and to configure synchronous-burst read characteristics of the flash device. all read configuration register bits are set and cleared using the program read configuration register command. section 9.3.2 describes how to program the read configuration register. upon power-up or exit from reset, the read configuration register defaults to asynchronous mode (rcr15 = 1; rcr[14:11] and rcr[9:0] are ignored). table 23 shows the read configuration register bit definitions. to read the rcr value, issue the read device information command to the desired partition. subsequent reads from the + 05h outputs rcr[15:0] on the data bus. table 22. clear status register command bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus clear status register device address 0050h --- ---
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 72 order number: 309823, revision: 003 9.3.1 latency count the latency count value programmed into rcr[14:11] is the number of valid clk edges from address-latch to the start of the data-output dela y. when the latency count has been satisfied, output data is driven after tchqv (see figure 50, ?latency count period? on page 73 ). table 23. read configuration register bit definitions read configuration register (rcr) default: cr15 = 1 read mode latency count wait polarit y r wait delay reserved burst length 15 14 13 12 11 10 9 8 7:3 2 1 0 bit name description 15 read mode 0 = synchronous burst-mode reads 1 = asynchronous page-mode reads (default) 14:11 latency count 00 1 1= code 3 01 0 0= code 4 01 0 1= code 5 01 1 0= code 6 01 1 1= code 7 10 0 0= code 8 10 0 1= code 9 10 1 0= code 10 10 1 1= code 11 11 0 0= code 12 (other bit settings are reserved) 10 wait polarity 0 =wait signal is active low (default) 1 =wait signal is active high 9 reserved write 0 to reserved bits 8wait delay 0 = wait de-asserted with valid data 1 = wait de-asserted one cycle before valid data (default) 7:3 reserved write 0 to reserved bits 2:0 burst length 01 0 = 8-word burst (wrap only) 01 1 = 16-word burst (wrap only) 11 1 = continuous-word burst (no-wrap; default) (other bit settings are reserved)
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 73 notes: 1. address latched on valid clock edge with adv# low and lc count begins. 2. address latched on adv# rising edge. lc count begins on subsequent valid clk edge. 9.3.2 programming the rcr the read configuration register (rcr) is programmed by issuing the program read configuration register command. this is a two-cycle command sequence requiring a setup command to be issued first, followed by a confirm command (see table 25 ). bus-write cycles to the flash device between the setup and confirm commands are not allowed ? a command sequence error will result. however, flash bus-read cycles between the setup and confirm commands are allowed. figure 50. latency count period adv#-l atch (2 ) clk latch (1) tchqv latency count latency count clk a dv# (1) a dv# (2) a[ma x:0 ] ce# oe# dq[15:0] table 24. clk frequencies for lc settings v ccq = 1.7 v to 2.0 v latency count setting frequency supported (mhz) 4 40 mhz 5 54 mhz 7 66 mhz 10 108 mhz 13 133 mhz table 25. program read configuration register command bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus program read configuration register register data 0060h register data 0003h
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 74 order number: 309823, revision: 003 to program the rcr, the desired settings for rcr[15:0] are placed on the address bus. the setup command (0060h) is driven on the data bus. upon issuing the setup command, the device/ addressed partition is automatically changed to read status register mode. next, the confirm command (0003h) is driven on the data bus. after issuing the confirm command, the addressed partition is automatically switched to read array mode. note: since the desired register value is placed on the address lines, any hardware-connection offsets between the host?s address outputs and the flash device?s address inputs must be considered. for example, if the host?s address outputs are aligned to the flash device?s address inputs such that host address bit a1 is connected to flash address bit a0, the desired register value may need to be left- shifted internally by one (example: 2532h becomes 4a64h) before programming the read configuration register. caution: care must be exercised when switching to synchronous mode. synchronous read accesses cannot occur until both the flash device and the memory controller?s chip select have reached synchronous operating mode. the software instructions used to perform the read configuration register programming sequence and the chip select configuration must be guaranteed not to fetch from the flash device, i.e., in system ram or locked in cache. this also applies when switching back to asynchronous mode from synchronous mode. 9.4 enhanced configuration register the enhanced configuration register (ecr) is a volatile 16-bit, read/write register used to select deep power down (dpd) operation and to modify the output-driver strength of the flash device. all enhanced configuration register bits are set and cleared using the program enhanced configuration register command. section 9.4.2 describes how to program the enhanced configuration register. upon power-up or exit from reset, the enhanced configuration register defaults to 0004h. table 26 shows the enhanced configuration register bit definitions. to read the value of the ecr, issue the read device information command to the desired partition. subsequent reads from the + 06h returns ecr[15:0]. table 26. enhanced configuration register bit definitions (sheet 1 of 2) enhanced configuration register default = 0004h deep power down (dpd) mode dpd polarity reserved output driver control 15 14 13:3 2 1 0 bit name description 15 deep power down (dpd) mode 0 = dpd disabled (default) 1 = dpd enabled
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 75 9.4.1 output driver control output driver control enables the user to adjust the device?s output-driver strength of the data i/o bus and wait signal. upon power-up or reset, ecr[2:0] defaults to an output impedance setting of 30 ohms. to change the output-driver strength, ecr[2:0] must be programmed to the desired setting as shown in table 27 . 9.4.2 programming the ecr the ecr is programmed by issuing the program enhanced configuration register command. this is a two-cycle command sequence requiring a setup command to be issued first, followed by a confirm command (see table 28 ). bus-write cycles to the flash device between the setup and confirm commands are not allowed ? a command sequence error will result. however, flash bus- read cycles between the setup and confirm commands are allowed. 14 dpd pin polarity 0 = active low (default) 1 = active high 13:3 reserved write 0 to reserved bits 2:0 output driver control 0 0 1 = code 1 0 1 0 = code 2 0 1 1 = code 3 1 0 0 = code 4 (default) 1 0 1 = code 5 1 1 0 = code 6 (other bit settings are reserved) table 26. enhanced configuration register bit definitions (sheet 2 of 2) enhanced configuration register default = 0004h deep power down (dpd) mode dpd polarity reserved output driver control 15 14 13:3 2 1 0 bit name description table 27. output driver control characteristics control bits ecr[2:0] impedance @ vccq/2 (ohm) driver multiplier load driven at same speed (pf) 001 90 1/3 10 010 60 1/2 15 011 45 2/3 20 100 (default) 30 1 30 101 20 3/2 35 11015240
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 76 order number: 309823, revision: 003 to program the enhanced configuration register, the desired settings for ecr[15:0] are placed on the address bus. the setup command (0060h) is driven on the data bus. upon issuing the setup command, the device/addressed partition is automatically changed to read status register mode. next, the confirm command (0004h) is driven on the data bus. after issuing the confirm command, the addressed partition is automatically switched to read array mode. this command functions independently of the applied v pp voltage. since the desired register value is placed on the address lines, any hardware-connection offsets between the host?s address outputs and the flash device?s address inputs must be considered, similar to programming the rcr. 9.5 read operations five types of data can be read from the device: array data, device information, cfi data, device status, and extended flash array (efa) data. upon power-up or return from reset, the device defaults to read array mode. to change the device?s read mode, the appropriate command must be issued to the device. table 29 shows the command codes used to configure the device for the desired read mode. the following sections describe each read mode. 9.5.1 read array upon power-up or exit from reset, the device defaults to read array mode. issuing the read array command places the addressed partition in read array mode. subsequent reads output array data. the addressed partition remains in read array mode until a different read command is issued, or a program or erase operation is performed in that partition, in which case, the read mode is automatically changed to read status. table 28. program enhanced configuration register command bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus program enhanced configuration register register data 0060h register data 0004h table 29. read mode command bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus read array partition address 00ffh --- --- read status register partition address 0070h --- --- read device information partition address 0090h --- --- cfi query partition address 0098h --- --- read extended flash array (efa) block partition address 0094h --- ---
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 77 to change a partition to read array mode while it is programming or erasing, first issue the suspend command. after the operation has been suspended, issue the read array command to the partition. when the program or erase operation is subsequently resumed, the partition will automatically revert back to read status mode. note: issuing the read array command to a partition that is actively programming or erasing causes subsequent reads from that partition to output invalid data. valid array data is output only after the program or erase operation has finished. the read array command functions independent of the voltage level on vpp. 9.5.2 read status register issuing the read status register command places the addressed partition in read status register mode. subsequent reads from that partition output status register information. the addressed partition remains in read status register mode until a different read-mode command is issued to that partition. performing a program, erase, or block-lock operation also changes the partition?s read mode to read status register mode. the status register is updated on the falling edge of ce#, or oe# when ce# is low. status register contents are valid only when sr7 = 1. the read status register command functions independent of the voltage level on vpp. 9.5.3 read device information issuing the read device information command places the addressed partition in read device information mode. subsequent reads output device information on the data bus. table 30 shows the address offset for reading the available device information. table 30. device information summary device information address bus data bus device manufacturer code (intel) partition base address + 00h 0089h device id code partition base address + 01h (see appendix b, ?device id codes.? ) main block lock status block base address + 02h d0 = lock status d1 = lock-down status efa block lock status block base address + 02h d4 = lock status d5 = lock-down status read configuration register partition base address + 05h configuration register data enhanced configuration register partition base address + 06h enhanced configuration register data otp lock register 0 partition base address + 80h lock register 0 data otp register - factory segment partition base address + 81h to 84h factory-programmed data otp register - user-programmable segment partition base address + 85h to 88h user data otp lock register 1 partition base address + 89h lock register 1 data otp registers 1 through 16 partition base address + 8ah to 109h user data
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 78 order number: 309823, revision: 003 the addressed partition remains in read device information mode until a different read command is issued. also, performing a program, erase, or block-lock operation changes the addressed partition to read status register mode. note: issuing the read device information command to a partition that is actively programming or erasing changes that partition?s read mode to read device information mode. subsequent reads from that partition will return invalid data until the program or erase operation has completed. the read device information command functions independent of the voltage level on vpp. 9.5.4 cfi query issuing the cfi query command places the addressed partition in cfi query mode. subsequent reads from that partition output cfi information (see appendix d, ?common flash interface? ). the addressed partition remains in cfi query mode until a different read command is issued, or a program or erase operation is performed, which changes the read mode to read status register mode. note: issuing the cfi query command to a partition that is actively programming or erasing changes that partition?s read mode to cfi query mode. subsequent reads from that partition will return invalid data until the program or erase operation has completed the cfi query command functions independent of the voltage level on vpp. 9.5.5 read extended flash array (efa) issuing the read extended flash array (efa) block command to a partition remaps that partition?s block addresses to corresponding efa block addresses. subsequent reads from that partition output efa data. the partition?s main flash array blocks are hidden until a read array command (ffh) is issued to that partition. data from efa blocks are read using single asynchronous or synchronous non-array reads only. note: issuing the read efa command to a partition that is actively programming or erasing changes that partition?s read mode to read efa mode. subsequent reads from that partition will return invalid data until the program or erase operation has completed. the read efa command functions independent of the voltage level on vpp. 9.6 programming modes each programming region in a flash block can be configured for one of two programming modes: control mode or object mode. programming mode is automatically set based on the data pattern upon the first program to a blank region. programming mode selection is driven primarily by the specific needs of the system with consideration given to two types of information: ? control: flash file system (ffs) or header, frequently changing code or data ? object: larger, infrequently changing code or data (e.g. objects or payloads) by implementing the appropriate programming mode, software can efficiently organize how information is stored in the flash memory array.
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 79 control mode programming regions and object mode programming regions can be intermingled within the same erase block. however, the programming mode of any region within a block can be changed only after erasing the entire block. the following sections describe the two programming modes. 9.6.1 control mode control mode programming is invoked when only the a-half (a3 = 0) of the programming region is programmed to 0s (refer to figure 52 ). the b-half (a3 = 1) remains erased. control mode allows up to 512 bytes of data to be programmed in the region. the information can be programmed in bits, bytes, or words. control mode supports the following programming methods: ? single-word programming (41h) ? buffered programming (e9h/d0h), and ? buffered enhanced factory programming (80h/d0h) figure 51. configurable programming regions . . flash array 256 programming regions per block flash block programming region in object mode programming region in control mode programming region in object mode programming region in object mode . . . 512 b 1 kb 256 kb 256 kb 256 kb . . 256 kb 256 kb . . . . . . . . . . . . . . . . . 256 kb 256 kb 256 kb . . 1 kb 1 kb . . .
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 80 order number: 309823, revision: 003 when buffered programming is used in control mode, all addresses must be in the a-half of the buffer (a3 = 0). during buffer fill, the b-half (a3 = 1) addresses do not need to be filled with 0xffff. control mode programming is useful for storing dynamic information, such as ffs headers, file info, etc. typically, it does not require the entire 512 bytes of data to be programmed at once. it may also contain data that is changed after initial programming using a technique known as ?bit twiddling?. header information can be augmented later with additional new information within a control mode-programmed region. this allows implementation of legacy file systems, as well as transaction-based power-loss recovery. in a control mode region, programming operations can be performed multiple times. however, care must be taken to avoid programming any zero?s in the b-half (a3 = 1) of the region. violation of this usage will cause sr4 and sr9 to be set, and the program operation will be terminated. see table 31, ?programming region next state table? on page 81 for details. 9.6.2 object mode object mode programming is invoked when one or more bits are programmed to zero in the b-half of the programming region (a3 = 1). object mode allows up to 1kb to be stored in a programming region. multiple regions are used to store more than 1kbyte of information. if the object is less than 1kbyte, the unused content will remain as 0xffff (erased). object mode supports two programming methods: ? buffered programming (e9h/d0h), and ? buffered enhanced factory programming (80h/d0h) single-word programming is not supported in object mode. to perform multiple programming operations within a programming region, control mode must be used. object mode is useful for storing static information, such as objects or payloads, that rarely change. figure 52. configured programming region in control mode segm ent 0 f f f f f f f f h eader seq table entry segm ent 31 f ile in fo h eader h eader dir info header h eader h eader 16b segm ent 2 segm ent 3 segm ent 30 segm ent 1 a half (a 3 = ?0 ?) f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f seq table entry h eader b half (a 3 = ?1 ?) 16b
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 81 once the programming region is configured in object mode, it cannot be augmented or over- written without first erasing the entire block containing the region. subsequent programming operations to a programming region configured in object mode will cause sr4 and sr8 to be set and the program operation to be terminated. see table 31, ?programming region next state table? on page 81 for details. note: issuing the 41h command to the b-half of an erased region will set error bits sr8 and sr9, and the programming operation will not proceed. see table 31, ?programming region next state table? on page 81 for more details. figure 53. configured programming region in object mode object object object object object object 32b (16 words) object object object segm ent 0 segm ent 31 segm ent 2 segment 3 segm ent 30 segment 1 1kb (512 words) object table 31. programming region next state table current state of programming region command issued 41h to b-half (a3 = 1) 41h to a-half (a3 = 0) e9h to b-half (a3 = 1) e9h to a-half (a3 = 0) erased program fail; illegal command sr[4,8,9] = 1 program successful sr[4,8,9] = 0 region configured to control mode program successful sr[4,8,9] = 0 region configured to object mode program successful sr[4,8,9] = 0 region configured to control mode control mode program successful sr[4,8,9] = 0 program fail; object data to control mode region sr[4,9] = 1 sr8 = 0 program successful sr[4,8,9] = 0 object mode program fail; rewrite to object mode region sr[4,8] = 1 sr9 = 0
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 82 order number: 309823, revision: 003 9.7 programming operations programming the flash array changes ?ones? to ?zeros?. to change zeros to ones, an erase operation must be performed (see section 9.8, ?block erase operations? ). only one programming operation can occur at a time. programming is permitted during erase suspend. information is programmed into the flash array by issuing the appropriate command. table 32 shows the two-cycle command sequences used for programming. caution: all programming operations require the addressed block to be unlocked, and a valid v pp voltage applied throughout the programming operation. otherwise, the programming operation will abort, setting the appropriate status register error bit(s). the following sections describe each programming method. 9.7.1 single-word programming main array programming is performed by first issuing the single-word program command. this is followed by writing the desired data at the desired array address. the read mode of the addressed partition is automatically changed to read status register mode, which remains in effect until another read-mode command is issued. note: issuing the read status register command to another partition switches that partition?s read mode to read status register mode, thereby allowing programming progress to be monitored from that partition?s address. single-word programming is supported in control mode only. the programming array address specified must be in the a-half of the programming region. during programming, the status register indicates a busy status (sr7 = 0b). upon completion, the status register indicates a ready status (sr7 = 1b). the status register should be checked for any errors, then cleared. the only valid commands during programming are read array, read device information, cfi query, read status and program suspend. after programming has finished, any valid command can be issued. table 32. programming commands bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus single-word program device address 0041h device address array data buffered program device address 00e9h device address 00d0h buffered enhanced factory program device address 0080h device address 00d0h efa program efa address 0044h efa address efa data
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 83 note: issuing the read array command to a partition that is actively programming causes subsequent reads from that partition to output invalid data. valid array data is output only after the program operation has finished. standby power levels are not realized until the programming operation has finished. asserting rst# immediately aborts the programming operation, and array contents at the addressed location are indeterminate. the addressed block should be erased, and the data re-programmed. 9.7.2 buffered programming buffered programming programs multiple words simultaneously into the flash memory array. data is first written to a write buffer and then programmed into the flash memory array in buffer-size increments. this can significantly reduce the effective word-write time. appendix c, ?flow charts? contains a flow chart of the buffered-programming operation. buffered programming is supported in both control mode and object mode. in object mode, the region must be programmed only once between erases. however in control mode, the region may be programmed multiple times. caution: when using the buffered program command in object mode, the start address must be aligned to the 512-word buffer boundary. in control mode, the programming array address specified must be in the a-half of the programming region. to perform a buffered programming operation, first issue the buffered program setup command at the desired starting address. poll sr7 to determine write-buffer availability (0 = not available, 1 = available). if the write buffer is not available, re-issue the setup command and check sr7; repeat until sr7 = 1. next, issue a word count at the desired starting address. the word count is the total number of words to be written into the write buffer, minus one. this value can range from 00h (one word) up to a maximum of 1ff (512 words). exceeding the allowable range causes the higher order data bits to be ignored. following the word count, subsequent bus-write cycles fill the write buffer with user-data up to the word count. note: user-data is programmed into the flash array at the address issued when filling the write buffer. the confirm command is issued after all user-data is written into the write buffer. the read mode of the device/addressed partition is automatically changed to read status register mode. if other than the confirm command is issued to the device, a command sequence error occurs and the operation aborts. after the confirm command has been issued, the write-buffer contents are programmed into the flash memory array. the status register indicates a busy status (sr7 = 0) during array programming. during array programming, the only valid commands are read array, read device information, cfi query, read status, and program suspend. after array programming has completed (sr7 = 1), any valid command can be issued. reading from another partition is allowed while data is being programmed into the flash memory array from the write buffer.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 84 order number: 309823, revision: 003 note: issuing the read array command to a partition that is actively programming or erasing causes subsequent reads from that partition to output invalid data. valid array data is output only after the program or erase operation has finished. upon completion of array programming, the status register indicates ready (sr7 = 1b). a full status register check should be performed to check for any programming errors. then the status register should be cleared using the clear status register command. a subsequent buffered programming operation can be initiated by issuing another setup command, and repeating the buffered programming sequence. any errors in the status register caused by the previous operation must be cleared to prevent them from masking any errors that may occur during the subsequent operation. 9.7.3 buffered enhanced factory programming (befp) buffered enhanced factory programming (befp) improves programming performance through the use of the write buffer, v pph and enhanced programming algorithm. user-data is written into the write buffer, then the buffer contents are automatically written into the flash array in buffer-size increments. befp is allowed in both control mode and object mode. the programming mode selection for the entire flash array block is driven by the specific type of information, e.g., header or object data. each 1kb of header or object data is configured to an aligned 1kb programming region to fill the entire main array block. the code/data pattern for headers does not contain zeros in the a3 = 1 addresses, and the code/data pattern for objects does contain zeros in the a3 = 1 addresses. internal verification during programming (inherent to mlc technology) and status register error checking are used to determine proper completion of the programming operation. this eliminates delays incurred when switching between single-word program and verify operations. befp consists of three distinct phases: 1. setup phase: v pph and block-lock checks 2. program/verify phase: buffered programming and verification 3. exit phase: block-error check appendix c, ?flow charts? contains a flow chart of the befp operation. table 33 lists specific befp requirements and considerations. notes: table 33. befp requirements and considerations befp requirements temperature (t case ) must be 25 c, 5 c voltage on v cc must be within the allowable operating range voltage on vpp must be within the allowable operating range 1 block being programmed must be erased and unlocked befp considerations block cycling below 100 erase cycles 2 reading from another partition during efp (rww) is not allowed befp programs within one block at a time befp cannot be suspended
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 85 1. v pp restrictions apply. see section 5.0, ?maximum ratings and operating conditions? . 2. recommended for optimal befp performance. if exceeded, some degradation in performance may occur, however, the internal algorithm will still function properly. 9.7.3.1 setup phase issuing the befp setup and confirm command sequence starts the befp algorithm. the read mode of the addressed partition is automatically changed to read status register mode. the address used when issuing the setup/confirm commands must be buffer-size aligned within the block being programmed -- buffer contents cannot cross block boundaries. caution: the read status register command must not be issued -- it will be interpreted as data to be written to the write buffer. a setup delay (t befp/setup ) occurs while the internal algorithm checks v pp and block-lock status. if errors are detected, the appropriate status register error bits are set and the operation aborts. the status register should be polled for successful befp setup, indicated by sr[7,0] = 0 (device busy, buffer ready for data). 9.7.3.2 program/verify phase data is first written into the write buffer, then programmed into the flash array. during the buffer- fill sequence, the address used must be buffer-size aligned. use of any other address will cause the operation to abort with a program fail error, and any data previously loaded in the buffer will not be programmed into the array. the buffer-fill data is stored in sequential buffer locations starting at address 00h. a word count equal to the maximum buffer size is used, therefore, the buffer must be completely filled. if the amount of data is less than the maximum buffer size, the remaining buffer locations must be ?padded? with ffffh to completely fill the buffer. flash array programming starts as soon as the write buffer is full. data words from the write buffer are programmed into sequential array locations. sr0 = 1 indicates the write buffer is not available while the befp algorithm programs the array. the status register should be polled for sr0 = 0 (buffer ready for data) to determine when the array programming has completed, and the write buffer is again available for loading. the internal address is automatically incremented to enable subsequent array programming to continue from where the previous buffer-fill/array-program sequence ended within the block. this cycle can be repeated to program the entire block. to exit the program/verify phase, write ffffh to an address outside of the block. 9.7.3.3 exit phase the status register should be polled for sr7 = 1 (device ready) indicating the befp algorithm has finished running, and the device has returned to normal operation. a full error check should be performed to ensure the block was programmed successfully.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 86 order number: 309823, revision: 003 9.7.4 efa word programming efa programming is performed by first issuing the efa program command. this is followed by writing the desired data at the desired efa address. this places the efa plane in the foreground in the addressed partition. the read mode of the addressed partition is changed to read status register mode, which remains in effect until another read-mode command is issued. note: issuing the read status register command to any other partition switches that partition?s read mode to the read status register, thereby allowing programming progress to be monitored from that partition?s address. during programming, the status register indicates a busy status (sr7 = 0). upon completion, the status register indicates a ready status (sr7 = 1). the status register should be checked for any errors, then cleared. issuing the efa program command outside of the efa block address range results in the status register indicating a program error. the only valid commands during programming are read array, read device information, cfi query, read status and program suspend. after programming has finished, any valid command can be issued. note: issuing the read array command to a efa-mapped partition that is actively programming causes subsequent reads from that partition to output invalid data. valid array data is output only after the program operation has finished. standby power levels are not be realized until the programming operation has finished. also, asserting rst# aborts the programming operation, and array contents at the addressed location are indeterminate. the addressed block should be erased, and the data re-programmed. 9.8 block erase operations erasing a block changes ?zeros? to ?ones?. to change ones to zeros, a program operation must be performed (see section 9.7, ?programming operations? ). erasing is performed on a block basis? an entire block is erased each time an erase command sequence is issued. once a block is fully erased, all addressable locations within that block read as logical ?ones? (ffffh). only one block-erase operation can occur at a time. a block-erase operation is not permitted during program suspend. to perform a block-erase operation, issue the block erase or efa block erase command sequence at the desired block address. table 34 shows the two-cycle block erase command sequence. table 34. block-erase command bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus block erase device address 0020h block address 00d0h efa block erase efa address 0024h efa block address 00d0h
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 87 erase operations performed on efa blocks are similar to erase operations performed on main-array blocks. issuing the efa block erase command places the efa plane in the foreground of the corresponding partition. issuing the efa block erase command outside of the efa plane?s address range causes the operation to abort, and the status register indicates an erase error (sr[7,5] = 1). caution: all block-erase operations require the addressed block to be unlocked, and a valid voltage applied to vpp throughout the block-erase operation. otherwise, the operation aborts, setting the appropriate status register error bit(s). the erase confirm command latches the address of the block to be erased. the addressed block is preconditioned (programmed to all zeros), erased, and then verified. the read mode of the addressed partition is automatically changed to read status register mode, and remains in effect until another read-mode command is issued. note: issuing the read status register command to another partition switches that partition?s read mode to the read status register, thereby allowing block-erase progress to be monitored from that partition?s address. sr0 indicates whether the addressed partition or other partition is erasing. during a block-erase operation, the status register indicates a busy status (sr7 = 0). upon completion, the status register indicates a ready status (sr7 = 1). the status register should be checked for any errors, and then cleared. if any errors did occur, subsequent erase commands to that partition are ignored unless the status register is cleared. the only valid commands during a block erase operation are read array, read device information, cfi query, read status and erase suspend. after the block-erase operation has completed, any valid command can be issued. note: issuing the read array command to a partition that is actively erasing a main block or efa block causes subsequent reads from that partition (or efa-mapped partition) to output invalid data. valid array data is output only after the block-erase operation has finished. standby power levels are not realized until the block-erase operation has finished. asserting rst# immediately aborts the block-erase operation, and array contents at the addressed location are indeterminate. the addressed block should be erased, and the data re-programmed. 9.9 blank check operation blank check is used to see if a main-array block is completely erased. blank check for efa blocks is not supported . a blank check operation is performed one block at a time, and cannot be used during program suspend or erase suspend. blank check speeds up flash programming and reclaim in customer manufacturing flows. automated programmer systems can use this one-step method instead of slower sequential reads of the entire block. this operation should not be used to determine erase-operation success or failure, such as after an aborted erase. to use blank check, first issue the blank check setup command (see table 35 ) followed by the confirm command. the read mode of the addressed partition is automatically changed to read status register mode, which remains in effect until another read-mode command is issued.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 88 order number: 309823, revision: 003 during a blank check operation, the status register indicates a busy status (sr7 = 0). upon completion, the status register indicates a ready status (sr7 = 1). note: issuing the read status register command to another partition switches that partition?s read mode to read status register mode, thereby allowing the blank check operation to be monitored from that partition?s address. the status register should be checked for any errors, and then cleared. if the blank check operation fails, i.e., the block is not completely erased, then the status register will indicate a blank check error (sr[7,5] = 1). the only valid command during a blank check operation is read status. blank check cannot be suspended. after the blank check operation has completed, any valid command can be issued. 9.10 suspend and resume program and erase operations of the main array or efa can be suspended to perform other device operations, and then subsequently resumed. however, otp register programming or blank check operations cannot be suspended. to suspend an on-going erase or program operation, issue the suspend command to any device address; the corresponding partition is not affected. table 36 shows the suspend and resume command bus-cycles. note: issuing the suspend command does not change the read mode of the partition. the partition will be in read status register mode from when the erase or program command was first issued, unless the read mode was changed prior to issuing the suspend command. the program or erase operation suspends at pre-determined points during the operation after a delay of t susp . suspend is achieved when sr[7,6] = 1 (erase-suspend) or sr[7,2] = 1 (program- suspend). note: throughout the block erase suspend or program suspend period, the addressed block must remain unlocked and a valid voltage applied to vpp. otherwise, the erase or program operation will abort, setting the appropriate status register error bit(s). also, wp# must remain unchanged. table 35. blank check command bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus blank check block address 00bch block address 00d0h table 36. suspend and resume command bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus suspend device address 00b0h --- --- resume device address 00d0h --- ---
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 89 asserting rst# aborts suspended block-erase and programming operations -- array contents at the addressed locations are indeterminate. the addressed block should be erased, and the data re- programmed. not all commands are allowed when the device is suspended. table 37 shows which device commands are allowed during program suspend or erase suspend. during suspend, main array-read and efa-read operations are not allowed in blocks being erased or programmed. also, programming operations are not allowed in blocks in erase-suspend state and if attempted, will result in status register program error to be set (sr4 = 1). a block-erase under program-suspend is not allowed. however, word-program under erase- suspend is allowed, and can be suspended. this results in a simultaneous erase-suspend/ program- suspend condition, indicated by sr[7,6,2] = 1. to resume a suspended program or erase operation, issue the resume command to any device address. the read mode of the resumed partition is unchanged; issue the read status register command to return the partition to read status mode. the operation continues where it left off, and the respective status register suspend bits are cleared. when the resume command is issued during a simultaneous erase-suspend/ program-suspend condition, the programming operation is resumed first. upon completion of the programming operation, the status register should be checked for any errors, and cleared. the resume command must be issued again to complete the erase operation. upon completion of the erase operation, the status register should be checked for any errors, and cleared. table 37. valid commands during suspend device command program suspend erase suspend read array allowed allowed read status register allowed allowed clear status register allowed allowed read device information allowed allowed cfi query allowed allowed word program / efa program not allowed allowed buffered program not allowed allowed buffered enhanced factory program not allowed not allowed block erase / efa erase not allowed not allowed program/erase suspend not allowed not allowed program/erase resume allowed allowed
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 90 order number: 309823, revision: 003 9.11 simultaneous operations the multi-partition architecture of the flash device allows programming or erasing to occur in one partition while reads are performed from another partition. only status reads are allowed in partitions that are busy programming or erasing. note: when otp register or efa commands are issued to any partition address, the otp register or efa plane is mapped onto that partition. table 38 shows the rules for reading from a partition while simultaneously programming or erasing within another partition. notes: 1. otp register, device information, cfi query, efa. table 38. read-while-program and read-while-erase rules read modes allowed when program/erase busy in partition a active operation read status array reads non-array reads 1 main-array program all partitions all partitions except busy partition a all partitions except busy partition a main-array erase all partitions all partitions except busy partition a all partitions except busy partition a otp register program all partitions all partitions except busy partition a not allowed efa program or erase all partitions all partitions except busy partition a not allowed table 39. simultaneous operation restrictions otp register or cfi parameter partition array data other partitions notes read (see notes) write/erase while programming or erasing in a main partition, the protection register or cfi data may be read from any other partition. reading the parameter partition array data is not allowed if the protection register or query data is being read from addresses within the parameter partition. (see notes) read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers or cfi data from parameter partition addresses is not allowed when reading array data from the parameter partition. read read write/erase while programming or erasing in a main partition, read operations are allowed in the parameter partition. accessing the protection registers or cfi data in a partition that is different from the one being programed/erased, and also different from the parameter partition is allowed. write no access allowed read while programming the protection register, reads are only allowed in the other main partitions. access to array data in the parameter partition is not allowed. programming of the protection register can only occur in the parameter partition, which means this partition is in read status. no access allowed write/erase read while programming or erasing the parameter partition, reads of the protection registers or cfi data are not allowed in any partition. reads in partitions other than the parameter partition are supported.
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 91 9.12 security the flash device incorporates features for protecting main-array contents and for implementing system-level security schemes. the following sections describe the available features. 9.12.1 block locking upon power up or exit from reset, all main array and efa blocks are locked, but not locked down. locked blocks cannot be erased or programmed. two methods of block-lock control are available: software and hardware. software control uses the block lock and block unlock commands; hardware control uses wp# along with the block lock- down command. block lock and unlock operations are independent of the voltage level on v pp . table 40 summarizes the command bus-cycles. to lock, unlock, or lock-down a block, first issue the setup command to any address within the desired block. the read mode of the addressed partition is automatically changed to read status register mode. next, issue the desired confirm command to the block?s address. note that the confirm command determines the operation performed. the status register should be checked for any errors, and then cleared. the lock status of a block can be determined by issuing the read device information command, and then reading from + 02h. dq0 indicates the lock status of the addressed block (0 = unlocked, 1 = locked), and dq1 indicates the lock-down status of the addressed block (0 = lock-down not issued; 1 = locked-down issued). section 9.5.3, ?read device information? on page 77 summarizes the details of this operation. blocks cannot be locked or unlocked while being actively programmed or erased. blocks can be locked or unlocked during erase-suspend, but not during program-suspend. note: if a block-erase operation is suspended, and then the block is locked or locked down, the lock status of the block will be changed immediately. when resumed, the erase operation will still complete. block lock-down protection is dependent on wp#. when wp# = v il , blocks locked down are locked, and cannot be unlocked using the block unlock command. when wp# = v ih , block lock- down protection is disabled - locked-down blocks can be individually unlocked using the block table 40. block locking command bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus lock block block address 0060h block address 0001h unlock block block address 0060h block address 00d0h lock-down block block address 0060h block address 002fh lock efa block block address 0064h block address 0001h unlock efa block block address 0064h block address 00d0h lock-down efa block block address 0064h block address 002fh
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 92 order number: 309823, revision: 003 unlock command. subsequently, when wp# = v il , previously locked-down blocks are once again locked and locked-down, including locked-down blocks that may have been unlocked while wp# was de-asserted. a locked-down block can only be unlocked by issuing the unlock block command with wp# deasserted. to return an unlocked block to the locked-down state, a lock-down command must be issued prior to asserting wp#. issuing the block lock-down command to an unlocked block does not lock the block. however, asserting wp# after issuing the block lock-down command locks (and locks down) the block. lock-down for all blocks is cleared upon power-up or exit from reset. figure 54 summarizes block- locking operations. notes: 1. [n,n,n] denotes logical state of wp#, dq1,and dq0, respectively; x = don?t care. 2. [0,1,1] states should be tracked by system software to differentiate between the hardware-locked state and the lock-down state. 9.12.2 one-time programmable (otp) registers the device contains seventeen 128-bit one-time programmable (otp) registers, and two 16-bit otp lock registers, as shown in figure 55, ?2-kbit otp registers? on page 93 . otp lock register 0 is used for locking otp register 0, and otp lock register 1 is used for locking otp registers 1 through 16. otp register 0 consists of two 64-bit segments: a lower segment that is pre-programmed with a unique 64-bit value and locked at the factory; and an upper segment that contains all ?ones? and is user-programmable. otp registers 1 through 16 contain all ?ones? and are user-programmable. figure 54. block locking operations locked [x,0,1] unlocked [x,0,0] locked down 2 [0,1,1] power up -or- exit from reset software locked [1,1,1] hardware locked 2 [0,1,1] unlocked [1,1,0] wp# = v il wp# = v ih software control (lock, unlock, lock-down command) hardware control (wp#)
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 93 each register contains otp bits that can only be programmed from ?one? to ?zero? - register bits cannot be erased from ?zero? back to ?one?. this feature makes the otp registers particularly useful for implementing system-level security schemes, for permanently storing data, or for storing fixed system parameters. otp lock register bits ?lock out? subsequent programming of the corresponding otp register. each otp register can be locked by programming its corresponding lock bit to zero. as long as an otp register remains unlocked (i.e., its lock bit = 1), any of its remaining ?one? bits can be programmed to ?zero?. caution: once an otp register is locked, it cannot be unlocked. attempts to program a locked otp register will fail with error bits set. to program any otp bits, first issue the program otp register setup command at any device address (see table 41 ). next, write the desired otp register data at the desired otp register address. otp register and otp lock register programming is performed 16 bits at a time; only ?zeros? within the data word affect any change to the otp register bits. figure 55. 2-kbit otp registers 0x89 otp lock register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x 10 2 0x 10 9 0x8a 0x91 128-bit otp register 16 (user-programmable) 128-bit otp register 1 (user-programmable) 0x88 0x85 64-bit segment (user-programmable) 0x84 0x81 0x80 otp lock register 0 64-bit segment (factory-programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit otp register 0
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 94 order number: 309823, revision: 003 attempting to program an otp register outside of the otp register space causes a program error (sr4 = 1). attempting to program a locked otp register causes a program error and a lock error (sr4 = 1, sr1 = 1). to read from any of the otp registers, first issue the read device information command. then read from the desired otp register address offset. for additional details, refer to section 9.5.3, ?read device information? on page 77 . 9.12.3 global main-array protection global main-array protection can be implemented by controlling v pp . when programming or erasing main-array or efa blocks, v pp must be equal to, or greater than, the lock-out voltage, v pplk . when v pp is below v pplk , program or erase operations are inhibited, thus providing absolute protection of the main array. various methods exist for controlling v pp , ranging from simple logic control to off-board voltage control. figure 56 shows example v pp supply connections that can be used to support program/ erase operations and main-array protection. table 41. program otp register command bus cycles command setup write cycle confirm write cycle address bus data bus address bus data bus program otp register device address 00c0h otp register address register data figure 56. example vpp supply connections vcc vpp v cc ? factory programming: vpp = v pph ? program/erase protection: vpp v pplk 10 ? vcc vpp v cc ? program/erase enable: prot# = v ih ? program/erase protection: prot# = v il prot# vcc vpp v cc ? low-voltage programming: vpp = v ppl -or- ? factory programming: vpp = v pph vcc vpp v cc ? low-voltage programming: vpp = v cc ? program/erase protection: none v pph v ppl v pph v ppl v ppl
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 95 appendix a device command codes a.1 flash command codes table 42. command bus operations (sheet 1 of 2) command code (setup/ confirm) description registers program read configuration register 0060h/ 0003h issuing this command sequence programs the read configuration register. the rcr value is placed on the address bus. program enhanced configuration register 0060h/ 0004h issuing this command sequence programs the enhanced configuration register. the ecr value is placed on the address bus. program otp register 00c0h issuing this command programs the protection registers or the lock registers associated with them. read modes read array 00ffh issuing this command places the addressed partition in read array mode. subsequent reads outputs array data. read status register 0070h issuing this command places the addressed partition in read status mode. subsequent reads outputs status register data. clear status register 0050h issuing this command clears all error bits in the status register. read device information 0090h issuing this command places the addressed partition in read device information mode. subsequent reads fr om specified address offsets outputs unique device information. cfi query 0098h issuing this command places the addressed partition in cfi query mode. subsequent reads from specified address offsets outputs cfi data. program/erase operations word program 0041h this command prepares the device for programming a single word into the flash array. on the next bus write cycle, the address and data are latched and written to the flash array. the addressed partition automatically switches to read status register mode. buffered program 00e9h/ 00d0h this command sequence initiates and executes a buffered programming operation. additional bus write/read cycles are required between the setup and confirm commands to properly perform this operation. the addressed partition automatically switches to read status register mode. buffered enhanced factory program 0080h/ 00d0h this command sequence initiates and executes a befp operation. additional bus write/read cycles are required after the confirm command to properly perform the operation. the addressed part ition automatically switches to read status register mode. block erase 0020h/ 00d0h issuing this command sequence erases the addressed block. the addressed partition automatically switches to read status mode. program/erase suspend 00b0h issuing this command to any device address initiates a suspend of a program or block-erase operation already in progress. sr6 = 1 indicates erase suspend, and sr2 = 1 indicates program suspend. program/erase resume 00d0h issuing this command to any device address resumes a suspended program or block-erase operation. a program suspend nested within an erase suspend is resumed first. blank check 00bch/ 00d0h this command sequence initiates the blank check operation on a block.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 96 order number: 309823, revision: 003 security lock block 0060h/ 0001h issuing this command sequence sets the lock bit of the addressed block. unlock block 0060h/ 00d0h issuing this command sequence clears the lock bit of the addressed block. lock down block 0060h/ 002fh issuing this command sequence locks down the addressed block. extended flash array read efa 0094h issuing this command places the addressed partition in read efa mode. subsequent reads outputs efa data. program efa 0044h this command prepares the device for programming a single word into the extended flash array. on the next bus write cycle, the address and data are latched and written to the efa. the addr essed partition automatically switches to read status register mode. erase efa 0024h/ 00d0h issuing this command sequence erases the addressed block in the efa. the addressed partition automatically switches to read status mode. lock efa block 0064h/ 0001h issuing this command sequence sets the lock bit of the addressed block in the efa. unlock efa block 0064h/ 00d0h issuing this command sequence clears the lock bit of the addressed block in the efa. lock down efa block 0064h/ 002fh issuing this command sequence locks down the addressed block in the efa. table 42. command bus operations (sheet 2 of 2) command code (setup/ confirm) description
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 97 appendix b device id codes the following table lists the device id codes for the intel strataflash ? cellular memory. table 43. device id codes density product device identifier code (hex) 512 mbit non-mux 887e ad-mux 8881 256 mbitt non-mux 8901 ad-mux 8904
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 98 order number: 309823, revision: 003 appendix c flow charts figure 57. word program for main array and efa flowchart program suspend loop star t write 0x41 or 0x44, word addr ess write d ata, word addr ess read status regi ster sr[7] = ful l status check (if desired) program complete suspend? 1 0 no yes word program procedure r epeat for subsequent wor d pr ogr am oper ati ons. full status r egi ster check can be done after each pr ogr am, or after a sequence of pr ogr am oper ati ons. write 0xff after the last operation to set to the read array state. comments bus operation command data = 0x41 or 0x44 addr = location to program wr i te program setup data = data to pr ogr am addr = location to program wr i te data status register data read n one check sr[7] 1 = wsm ready 0 = wsm busy idle n one (setup) (confi rm) full status check procedure read status regi ster program successful sr[3] = sr[1] = 0 0 sr[4] = 0 1 1 1 v pp range error device protect err or pr ogr am error sr[3] m ust be cl ear ed befor e the wr i te state machi ne wi l l allow further program attempts. if an er r or i s detected, cl ear the status register befor e continui ng oper ati ons - onl y the cl ear staus register command clears the status register error bits. idle idle bus operation n one n one command check sr[3]: 1 = v pp error check sr[4]: 1 = data pr ogr am er r or comments idle n one check sr[1]: 1 = bl ock l ocked; oper ati on abor ted
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 99 figure 58. program suspend/resume flowchart read status register sr.7 = sr.2 = write ffh susp partition read array data pr ogr am completed done reading write ffh pgm' d partition wr i te d 0h any address program resumed read ar r ay data 0 no 0 yes 1 1 program suspend / resume procedure write program resume data = d0h addr = suspended bl ock ( ba) bus operat ion command comments write program suspend data = b0h addr = bl ock to suspend ( ba) standby check sr.7 1 = wsm r eady 0 = wsm busy standby check sr.2 1 = pr ogr am suspended 0 = pr ogr am com pl eted write read array data = ffh addr = any addr ess wi thi n the suspended par tition read read arr ay data from block other than the one bei ng pr ogr amm ed read status register data addr = suspended bl ock ( ba) pgm_sus.wmf start wr i te b0h any address program suspend read status program resume read array read array wr i te 70h same partition write read status data = 70h addr = sam e par ti ti on if the suspended partition was placed in read array mode: write read status return partition to status mode: data = 70h addr = sam e par ti ti on wr i te 70h same partition read status
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 100 order number: 309823, revision: 003 figure 59. buffered program flowchart write confirm 0xd0 and block address buffer program data, word address x = 0 abort buffer program? no x = n? write buffer data, word address x = x + 1 write to another block address buffer program aborted no yes yes write word count-1, buffer address suspend program loop read status register sr[7] =? full status check if desired program complete suspend program? 1 0 yes no buffer programming procedure no other write commands except buffer write are allowed during this period. current and other partitions of the device can be read by addressing the location in other partition and driving oe# low. commands may be issued to the device. flash ready? sr[7] = timeout? 0 = n o 1 = yes issue read status register command at partition address yes n o issue buffer prog. cmd. 0xe9, block address set timeout or loop counter issue read array command at partition address timeout error 1 = yes notes: 1. the device outputs the status register when read. 2. the device outputs the array data when read . 3. buffer programming is available in the main array only. this algorithm may be used for object mode or control mode programming. upon issuing 0xe9 the partition state does not change. 4. word count value on d[8:0] is loaded into the word count register. count ranges for this device are n = 0x000 to 0x1ff. 5. buffer address on a[max:9] specifies a single 512-word buffer-size array region. this is latched and held constant during the entire operation. 6. the word address within the buffer, specified by a [8:0], is provided. upper address bits are ignored. 7. the device aborts the buffer program command if the current address is outside the original block address. 8. upon issuing 0xd0 the partition is placed in status read mode. if block address changes, buffer program will abort. 9. the status register indicates an improper command sequence if the buffer program command is aborted; use the clear status register command to clear error bits. full status check can be done after all erase and write sequences complete. write 0xff after the last operation to place the partition in the read array state. write (note 1) standby read (note 9) read status none none idle none write (note 2) read array write (note 3) buffer prog. setup data = 0x70 addr = block address check sr[7]: 1 = wsm ready 0 = wsm busy status register data addr = block address check sr[7]: 1 = write buffer available 0 = no write buffer available data = 0xff addr = block address data = 0xe9 addr = block address write (note 8) buffer prog. conf. data = 0xd0 addr = block address write (notes 4,5) none data = n = word count - 1 (n = 0 corresponds to count = 1) addr = buffer address write (notes 6, 7) none data = write buffer data addr = word address write (notes 6, 7) none data = write buffer data addr = word address bus operation command comment s
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 101 figure 60. buffered efp flowchart write data @ 1 st word address last data? write 0xffff, address not within current block program done ? read status reg . y no (sr [7]=0) full status check procedure program complete read status reg . befp exi ted ? yes (sr [7]=1 ) start write 0x80 @ 1 st word address v pp applied , block unlocked write 0xd0 @ 1 st word address befp setup done ? read status reg . exit n program & verify phase exit phase setup phase buffered enhanced factory programming (buffered-efp) procedure x = 512 ? initialize count : x = 0 increm ent count : x = x +1 y notes: 1. befp is available in the main array only . 2. first-word address to be program med within the target block m ust be aligned on a write -buffer boundary . 3. w rite-buffer contents are program med sequentially to the flash array starting at the first word address ; wsm internally incr ements addressing . n check v pp , lock errors (sr[3,1]) yes (sr[7]=0) comments bus state operat ion befp setup delay data stream ready repeat for subsequent blocks ; after befp exit , a full status register check can determine if any program error occurred ; see full status register check procedure in the word program flowchart . w r i te 0 xf f to enter r ead ar ray state . check sr [7]: 0 = exit not completed 1 = exit completed check exit status read status register data = status reg . data address = 1st w ord addr befp exit standby if sr[7] is set, check: sr[3] set = v pp error sr[1] set = locked block error condition check standby check sr [7]: 0 = befp ready 1 = befp not ready befp setup done ? standby data = status reg . data address = 1 st word addr status register read data = 0xd0 @ 1 st w ord address befp confirm write data = 0x80 @ 1 st word address befp setup write (note 2) v pph applied to vpp unlock block write befp setup bus st at e comments operation no (sr[0]=1) yes (sr[0]=0 ) no (sr[7]=1) befp program & verify comments b u s st at e operation write (note 3) load buffer standby increment count standby initialize count data = data to program address = 1 st word addr . x = x+1 x = 0 standby buffer full? x = 512? yes = read sr [0] no = load next data w ord read standby status register data stream ready ? data = status register data address = 1 st word addr . check sr [0]: 0 = ready for data 1 = not ready for data read standby standby write status register program done ? last data? exi t pr og & verify phase data = status reg . data address = 1 st word addr . check sr [0]: 0 = program done 1 = program in progress no = fill buffer again yes = exit d ata = 0 xff f f @ addr ess not i n current block
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 102 order number: 309823, revision: 003 figure 61. block erase for main array and efa flowchart star t full erase status check procedure repeat for subsequent block erasures. ful l status r egister check can be done after each block er ase or after a sequence of bl ock er asur es. wr i te 0xff after the l ast oper ation to enter r ead ar r ay mode. sr [1,3] must be clear ed befor e the wr ite state m achi ne w il l allow further erase attempts. only the clear status register command clear s sr[1, 3, 4, 5]. if an error is detected, clear the status register before attempting an erase retry or other error recovery. no suspend er ase 1 0 0 0 1 1,1 1 1 0 yes suspend erase loop 0 wr i te 0x20 or 0x24 block address write 0xd0, block address read status register sr[7] = full erase status check (if desired) block er ase complete read status register block er ase successful sr[1] = block locked error block erase procedure bus operation command comments write bl ock er ase setup data = 0x20 or 0x24 addr = block to be er ased ( ba) write er ase confirm data = 0xd0 addr = block to be er ased ( ba) read none status register data. idle none check sr[7]: 1 = wsm ready 0 = wsm busy bus operation command comments sr[3] = v pp range error sr[4,5] = command sequence er r or sr[5] = block erase error idle none check sr[3]: 1 = v pp range er r or idle none check sr[4,5]: both 1 = comm and sequence er r or idle none check sr[5]: 1 = block erase error idle none check sr[1]: 1 = attempted er ase of l ocked bl ock; er ase abor ted. (bl o ck era se) (erase confi rm)
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 103 figure 62. erase suspend/resume flowchart er ase completed read ar r ay data 0 0 no read 1 program program loop read ar ray data 1 start read status regi ster sr[7] = sr[6] = er ase resumed read or program? done wr i te wr i te idle idle wr i te er ase suspend read ar r ay or pr ogr am none none pr ogr am resume data = 0xb0 addr = same par ti tion addr ess as above data = 0xff or 0x40 addr = any addr ess wi thin the suspended par ti tion check sr[7]: 1 = wsm r eady 0 = wsm busy check sr[6]: 1 = er ase suspended 0 = erase completed data = 0xd0 addr = any addr ess bus operation command comments read none status register data. addr = same par ti tion read or wr i te none read ar r ay or pr ogr am data fr om/to bl ock other than the one being er ased erase suspend / resume procedure if t he suspended part it ion was placed in read array mode or a program loop: wr ite 0xb0, any addr ess (e ra se susp end ) wr ite 0x70, sam e partition (read status) wr ite 0xd0, any addr ess (erase resume) wr ite 0x70, sam e partition (read status) wr ite 0xff, erased partition (read array) wr i te read status data = 0x70 addr = any parti ti on addr ess wr i te read status register retur n par ti tion to status m ode: data = 0x70 addr = same par ti tion
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 104 order number: 309823, revision: 003 figure 63. main array and efa block lock operations flowchart no start wr i te 0x60 or 0x64, bl ock addr ess wr i te 0x90 read bl ock lock status locking change? lock c hange complete wr ite either 0x01/0xd0/0x2f, bl ock addr ess write 0xff partition address yes wr i te wr i te wr i te ( opti onal ) read ( opti onal ) idle wr i te lock setup lock, unlock, or lock-down confirm read device id bl ock lock status none read main array data = 0x60 or 0x64 addr = block to lock/unlock/lock-down data = 0x01 (block lock) 0xd0 (block unlock) 0x2f (lock-down block) addr = block to lock/unlock/lock-down data = 0x90 addr = bl ock addr ess + offset 2 block lock status data addr = bl ock addr ess + offset 2 confir m locking change on d[1,0] . data = 0xff addr = bl ock addr ess bus operation command comments locking operations procedure (l ock con fi rm) (read de vi ce id) (read main array) o ptional (l ock s etu p)
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 105 figure 64. protection register programming flowchart full status check procedure pr ogr am pr otecti on regi ster oper ati on addr esses must be wi thi n the pr otecti on register addr ess space. addr esses outside this space will return an error. repeat for subsequent pr ogr am mi ng oper ati ons. ful l status regi ster check can be done after each pr ogr am, or after a sequence of program operations. wr ite 0xff after the last operation to set read array state. sr[3] must be cleared before the write state machine will allow fur ther program attempts. only the cl ear staus r egi ster comm and cl ear s sr[1, 3, 4]. if an er r or is detected, cl ear the status r egi ster befor e attempting a program retry or other error recovery. 1 0 1 1 1 protection register programming procedure start wr i te 0xc0, pr address wr ite pr address & data read status register sr[7] = full status check (if desired) program complete read status register data program successful sr[3] = sr[4] = sr[1] = v pp range er r or program error register locked; program aborted idle idle bus operat ion none none command check sr[3]: 1 = v pp range er r or check sr[4]: 1 = programming error comments write write idle program pr setup pr otecti on program none data = 0xc0 addr = first location to program data = data to program addr = locati on to pr ogr am check sr[7]: 1 = wsm ready 0 = wsm busy bus operat ion command comments read none status register data. idle none check sr[1]: 1 = block locked; operation aborted (program setup) (confirm data) 0 0 0
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 106 order number: 309823, revision: 003 figure 65. blank check operation flowchart start full blank check status check procedure no 1 0 write 0xbc, block address write 0xd0, block address read status register sr[7] = full blank check status read blank check blank check procedure bus operation command comments write blank check setup data = 0xbc addr = block to be read (ba) write blank check confirm data = 0xd0 addr = block to be read (ba) read none status register data. idle none check sr[7]: 1 = wsm ready 0 = wsm busy 0 sr[1,3] must be cleared before the write state machine will allow blank check to be performed. only the clear status register command clears sr[1, 3, 4, 5]. if an error is detected, clear the status register before attempting a blank check retry or other error recovery. 0 0 1,1 1 read status register blank check successful bus operation command comments sr[4,5] = command sequence error sr[5] = blank check error idle none check sr[4,5]: both 1 = command sequence error idle none check sr[5]: 1 = blank check error repeat for subsequent block blank check. full status register check should be read after blank check has been performed on each block.
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 107 appendix d common flash interface the common flash interface (cfi) is part of an overall specification for multiple command-set and control-interface descriptions. this appendix describes the database structure containing the data returned by a read operation after issuing the cfi query command (see section 9.5.4, ?cfi query? on page 78 ). system software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. the system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. d.2 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device?s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (a/dq 7-0 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ?q? and ?r,? appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. the device outputs ascii ?q? in the low byte (a/dq 7-0 ) and 00h in the high byte (a/dq 15-8 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word-wide devices is always ?00h,? the leading ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table 44. summary of query structure output as a function of device and mode device hex offset hex code ascii device addresses 00010: 51 ?q? 00011: 52 ?r?
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 108 order number: 309823, revision: 003 d.3 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. block erase status (bsr[1]) allows system software to determine the success of the last block erase operation. bsr[1] can be used just after power-up to verify that the vcc supply was not accidentally removed during an erase operation. only issuing another operation to the block resets this bit. the block status register is accessed from word address 02h within each block. table 45. example of query structure output of x16 devices word addressin g : b y te addressin g : offset hex code value offset hex code value a x ?a 0 d 15 ? d 0 a x ?a 0 d 7 ? d 0 00010h 0051 "q" 00010h 51 "q" 00011h 0052 "r" 00011h 52 "r" 00012h 0059 "y" 00012h 59 "y" 00013h p_id lo prvendor 00013h p_id lo prvendo r 00014h p_id hi id # 00014h p_id lo id # 00015h p lo prvendor 00015h p_id hi id # 00016h p hi tblad r 00016h ... ... 00017h a _id lo altvendor 00017h 00018h a _id hi id # 00018h table 46. block status register offset len g th description a dd. v alue (ba+2)h (1) 1 block lock status register ba+2 --00 or --01 ba+2 (bit 0): 0 or 1 ba+2 (bit 1): 0 or 1 ba+2 (bit 4): 0 or 1 ba+2 (bit 5): 0 or 1 bsr 2?3, 6-7: reserved for future use ba+2 (bit 2?3, 6-7): 0 bsr.4 efa block lock status 0 = unlocked 1 = locked bsr.5 efa block lock-down status 0 = not locked down 1 = locked down bsr.0 block lock status 0 = unlocked 1 = locked bsr.1 block lock-down status 0 = not locked down 1 = locked down 1. ba = the beginning location of a block address (i.e., 020000h is block 1?s (256kb block) beginning location in word mode)
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 109 d.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). table 47. cfi identification offset length description add. hex code value 10h 3 query-unique ascii string ?qry? 10: --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interface id code. 13: --00 16-bit id code for vendor-specified algorithms 14: --02 15h 2 extended query table primary algorithm address 15: --0a 16: --01 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 table 48. system interface information offset length description add. hex code v alue 1bh 1 1b: --17 1.7v 1ch 1 1c: --20 2.0v 1dh 1 1d: --85 8.5v 1eh 1 1e: --95 9.5v 1fh 1 ?n? such that t yp ical sin g le word p ro g ram time-out = 2 n s 20h 1 ?n? such that t yp ical full buffer write time-out = 2 n s 21h 1 ?n? such that t yp ical block erase time-out = 2 n m-sec 21: --0a 1s 22h 1 ?n? such that t yp ical full chi p erase time-out = 2 n m-sec 22: --00 na 23h 1 ?n? such that maximum word p ro g ram time-out = 2 n times t yp ical 23: --02 256 s 24h 1 ?n? such that maximum buffer write time-out = 2 n times t yp ical 24: --02 8192 s 25h 1 ?n? such that maximum block erase time-out = 2 n times t yp ical 25: --02 4s 26h 1 ?n? such that maximum chi p erase time-out = 2 n times t yp ical 26: --00 na v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 110 order number: 309823, revision: 003 d.5 device geometry definition table 49. device geometry definition offset len g th description code 27h 1 ?n? such that device size = 2 n in number of bytes 27: see table below 7654321 0 28h 2 ? ? ? ? x64 x32 x16 x8 28: --01 x16 15 14 13 12 11 10 9 8 ??????? ? 29:--00 2ah 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: --0a 1024 2b: --00 2ch 1 2c: 2dh 4 erase block region 1 information 2d: bits 0?15 = y, y+1 = number of identical-size erase blocks 2e: bits 16?31 = z, region erase block(s) size are z x 256 bytes 2f: 30: 31h 4 reserved for future erase block region information 31: 32: 33: 34: 35h 4 reserved for future erase block region information 35: 36: 37: 38: see table below see table below see table below see table below flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region figure 66. device geometry definition (continued) ?b ?t ?b ?t --19 --1a --01 --01 --00 --00 --0a --0a --00 --00 --01 --01 --7f --ff --00 --00 --00 --00 --04 --04 256 mbit 512 mbit address 27: 28: 29: 2a: 2b: 2c: 2d: 2e: 2f: 30:
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 111 d.6 intel-specific extended query table table 50. primary vendor-specific extended query offset (1) length description hex p = 10ah (optional flash features and commands) add. code v alue (p+0)h 3 primary extended query table 10a --50 "p" (p+1)h unique ascii string ?pri? 10b: --52 "r" (p+2)h 10c: --49 "i" (p+3)h 1 major version number, ascii 10d: --31 "1" (p+4)h 1 minor version number, ascii 10e: --34 "4" --e6 (non-mux) (p+5)h 4 optional feature and command support (1=yes, 0=no) 10f: --66 (ad-mux) (p+6)h bits 10?31 are reserved; undefined bits are ?0.? if bit 31 is 110: --07 (p+7)h ?1? then another 31 bit field of optional features follows at 111: --00 (p+8)h the end of the bit?30 field. 112: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 0 no bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 1 yes bit 6 otp bits supported bit 6 = 1 yes bit 7 pagemode read supported bit 7 = 0 no (ad-mux) yes (non-mux) bit 8 synchronous read supported bit 8 = 1 yes bit 9 simultaneous operations supported bit 9 = 1 yes bit 10 extended flash array blocks supported bit 10 = 1 yes bit 30 cfi link(s) to follow bit 30 = 0 no bit 31 another "optional features" field to follow bit 31 = 0 no (p+9)h 1 113: --01 bit 0 program supported after erase suspend bit 0 = 1 yes (p+a)h 2 block lock status register mask 114: --33 (p+b)h bits 2-3, 6-15 are reserved; undefined bits are ?0? 115: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 1 yes bit 4 efa block lock-bit status register active bit 4 = 1 yes bit 5 efa block lock-down bit status active bit 5 = 1 yes (p+c)h 1 116: --18 1.8v (p+d)h 1 117: --90 9.0v supported functions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts v cc logic supply highest performance program/erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 112 order number: 309823, revision: 003 table 51. otp register information p = 10ah (optional flash features and commands) add. code v alue (p+e)h 1 118: --02 2 (p+f)h 4 otp field 1: otp description 119: --80 80h (p+10)h this field describes user-available one time programmable 11a: --00 00h (p+11)h (otp) register bytes. some are pre-programmed 11b: --03 8 byte (p+12)h 11c: --03 8 byte (p+13)h 10 otp field 2: otp description 11d: --89 89h (p+14)h 11e: --00 00h (p+15)h 11f: --00 00h (p+16)h 120: --00 00h (p+17)h 121: --00 0 (p+18)h bits 40?47 = ?n? n = factory pgm'd groups (high byte) 122: --00 0 (p+19)h 123: --00 0 (p+1a)h 124: --10 16 (p+1b)h 125: --00 0 (p+1c)h 126: --04 16 bits 0?31 point to the otp register physical lock-word address in the jedec- plane. following bytes are factory or user-programmable. bits 32?39 = ?n? n = factory pgm'd groups (low byte) bits 48?55 = ?n? \ 2n = factory programmable bytes/group bits 56?63 = ?n? n = user pgm'd groups (low byte) number of otp register fields in jedec id space. ?00h,? indicates that 256 otp fields are available with device-unique serial numbers. others are user programmable. bits 0?15 point to the otp register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user-programmable. bits 0?7 = lock/bytes jedec-plane physical low address bits 8?15 = lock/bytes jedec-plane physical high address bits 16?23 = ?n? such that 2 n = factory pre-programmed bytes bits 24?31 = ?n? such that 2 n = user programmable bytes bits 64?71 = ?n? n = user pg m'd g rou p s ( hi g h b y te ) bits 72?79 = ?n? 2 n = user programmable bytes/group table 52. burst read information offset (1) length description hex p = 10ah (optional flash features and commands) add. code v alue (p+1d)h 1 127: --05 (non-mux) --00 (ad-mux) 32-byte (non-mux) 0 (ad-mux) (p+1e)h 1 128: --03 3 (p+1f)h 1 129: --02 8 (p+20)h 1 synchronous mode read capability configuration 2 12a: --03 16 (p+21)h 1 synchronous mode read capability configuration 3 12b: --07 cont page mode read capability bits 0?7 = ?n? such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read p a g e buffer. number of synchronous mode read configur ation fields that follow. 00h indicates no burst capability. synchronous mode read capability configuration 1 bits 3?7 = reserved bits 0?2 ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit va lue can be written directly to the read configuration register bits 0?2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data out p ut width.
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 113 table 53. partition and erase block information table 54. partition region 1 information offset (1) see table below p = 10ah description a ddress bottom top ( optional flash features and commands ) len bot top (p+22)h (p+22)h 112c:12c: number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions. (p+23)h (p+23)h data size of this parition region information field 2 12d: 12d (p+24)h (p+24)h (# addressable locations, including this field) 12e 12e (p+25)h (p+25)h number of identical partitions w ithin the partition region 2 12f: 12f: (p+26)h (p+26)h 130: 130: (p+27)h (p+27)h 1131:131: (p+28)h (p+28)h 1132:132: (p+29)h (p+29)h 1133:133: (p+2a )h (p+2a )h 1134:134: (p+2b)h (p+2b)h partition region 1 erase block type 1 information 4 135: 135: (p+2c)h (p+2c)h bits 0?15 = y, y+1 = # identical-size erase blks in a partition 136: 136: (p+2d)h (p+2d)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 137: 137: (p+2 e)h (p+2 e)h 138: 138: (p+2f)h (p+2f)h partition 1 (erase block type 1) 2139:139: (p+30)h (p+30)h block erase cycles x 1000 13a : 13a : (p+31)h (p+31)h 113b:13b: (p+32)h (p+32)h 113c:13c: partition region 1 (erase block type 1) programming region information 6 (p+33)h (p+33)h bits 0?7 = x, 2^x = programming region aligned size ( bytes )13d: 13d: (p+34)h (p+34)h bits 8?14 = reserved; bit 15 = legacy flash operation (ignore 0:7) 13e: 13e: (p+35)h (p+35)h bits 16?23 = y = control mode v a lid size in bytes 13f: 13f: (p+36)h (p+36)h bits 24-31 = reserved 140: 140: (p+37)h (p+37)h bits 32-39 = z = control mode in v a lid s iz e in b y te s 1 4 1 : 141: (p+38)h (p+38)h bits 40-46 = reserved; bit 47 = legacy flash operation (ignore 23:16 & 39:32) 142: 142: partition 1 (erase block type 1) bits per cell; internal eda c bits 0?3 = bits per cell in erase region b it 4 = in te rn a l ed a c u s e d ( 1 =y e s , 0 =n o ) b its 5 ? 7 = re s e rv e f o r f u tu re u s e number of program or erase operations allow ed in a partition bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allow ed in other partitions w hile a p a rtitio n in th is re g io n is in pro g ra m m o d e bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allow ed in other partitions w hile a partition in this region is in erase mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w / contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) +? + (type n blocks)x(type n block sizes) partition 1 (erase block type 1) page mode and synchronous mode capabilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host w rites permitted (1=yes, 0=no) b its 3 ? 7 = re s e rv e d f o r f u tu r e u s e
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 114 order number: 309823, revision: 003 table 55. extended flash array partition and erase block information figure 67. extended flash array partition region 1 information offset (1) see table below 0 descri p tion a ddress bottom to p ( o p tional flash features and commands ) len bot top (p+39)h (p+39)h 1 143: 143: number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions. (p+3a)h (p+3a)h data size of this parition region information field 2 144: 144 (p+3b)h (p+3b)h (# addressable locations, including this field) 145 145 (p+3c)h (p+3c)h number of identical partitions within the partition region 2 146: 146: (p+3d)h (p+3d)h 147: 147: (p+3e)h (p+3e)h 1 148: 148: (p+3f)h (p+3f)h 1 149: 149: (p+40)h (p+40)h 1 14a: 14a: (p+41)h (p+41)h 1 14b: 14b: (p+42)h (p+42)h efa partition region erase block type 1 information 4 14c: 14c: (p+43)h (p+43)h bits 0?15 = y, y+1 = # identical-size erase blks in a partition 14d: 14d: (p+44)h (p+44)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 14e: 14e: (p+45)h (p+45)h 14f: 14f: (p+46)h (p+46)h efa (erase block type 1) 2 150: 150: (p+47)h (p+47)h block erase cycles x 1000 151: 151: (p+48)h (p+48)h 1 152: 152: (p+49)h (p+49)h 1 153: 153: efa (erase block type 1) programming region information 4 (p+4a)h (p+4a)h bits 0?7 = y , 2^ y = pro g rammin g re g ion ali g ned size ( b y tes ) 154: 154: (p+4b)h (p+4b)h bits 8?14 = reserved; bit 15 = legacy flash operation (ignore 0:7) 155: 155: (p+4c)h (p+4c)h bits 16?23 = y = control mode valid size in b y tes 156: 156: (p+4d)h (p+4d)h bits 24-31 = reserved 157: 157: (p+4e)h (p+4e)h bits 32-39 = z = control mode invalid size in b y tes 158: 158: (p+4f)h (p+4f)h bits 40-46 = reserved; bit 47 = legacy flash operation (ignore 23:16 & 39:32) 159: 159: efa (erase block type 1) bits per cell; internal edac bits 0?3 = bits per cell in erase region bit 4 = internal edac used (1=yes, 0=no) bits 5?7 = reserve for future use efa (erase block type 1) pagemode and synchronous mode capabilities as defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3?7 = reserved for future use number of program or erase operations allowed in a partition bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in program mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allowed in other partitions while a partition in this region is in erase mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) +?+ (type n blocks)x(type n block sizes)
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 115 table 56. partition and erase block region information a ddres s 256 mbit ?b ?t ?b ?t 12c: --01 --01 12d: --16 --16 12e: --00 --00 12f: --08 --08 130: --00 --00 131: --11 --11 132: --00 --00 133: --00 --00 134: --01 --01 135: --0f --1f 136: --00 --00 137: --00 --00 138: --04 --04 139: --64 --64 13a: --00 --00 13b: --12 --12 13c: --02 (ad-mux) --02 (ad-mux) --03 (non-mux) --03 (non-mux) 13d: --0a --0a 13e: --00 --00 13f: --10 --10 140: --00 --00 141: --10 --10 142: --00 --00 143: --01 --01 144: --16 --16 145: --00 --00 146: --01 --01 147: --00 --00 148: --11 --11 149: --00 --00 14a: --00 --00 14b: --01 --01 14c: --03 --03 14d: --00 --00 14e: --20 --20 14f: --00 --00 150: --64 --64 151: --00 --00 152: --01 --01 153: --02 (ad-mux) --02 (ad-mux) --03 (non-mux) --03 (non-mux) 154: --00 --00 155: --80 --80 156: --00 --00 157: --00 --00 158: --00 --00 159: --80 --80 512 mbit
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 116 order number: 309823, revision: 003 appendix e next state table table 57 through table 62 show the command state transitions (next state table) based on incoming commands. only one partition can be actively programming or erasing at a time. each partition stays in its last read state (read array, read device id, read cfi, read efa or read status register) until a new command changes it. the next state does not depend on the partition?s output state. table 57. next state table (sheet 1 of 6) re ad a rray ( 3 ) read efa word prog ram (4,5,12) pr o g r a m ef a write to buffered pr o g r a m (bp) eras e se tu p (4,5,12) efa b lo c k eras e setup buffered enhanc ed fac tory pg m s e tu p (4 , 12 ) be confirm, blank check co nf irm p/e re s u me , ul b con f irm (9) bp / pr g / erase suspend re ad status clear status register (6) (ffh) (94h) (41h) (44h) (e9h) (20h) (24h) (80h) (d0h) (b0h) (70h) (50h) prog ram setup ef a pr o g r a m setup bp setup erase setup efa b lo c k eras e setup befp setup read y (unlock block) read y (unlock block) setup busy is i n o t p b us y is i n o t p b us y otp busy is in o tp b u s y setup busy pr o g r a m busy program busy word pgm suspend illegal state (is) in pgm busy suspend pr o g r a m suspend program busy word prog ram suspend ( error bits cleared ) illegal state (is) in pgm suspend setup bp load 1 (10) bp load 2 (10) bp confirm bp busy bp bus y bp bus y bp bus y bp suspend ille g a l s ta te in b p b u s y bp suspend bp suspend bp busy bp suspend ( error bits cleared ) illegal state in bp sus pend setup eras e bu s y busy erase bus y eras e busy eras e suspend illegal state(is) in erase busy suspend word pr o g r a m setup in erase sus pend efa w ord prog ram in erase suspend bp setup in eras e suspend eras e bu s y er a s e suspend ( error bits cleared ) illegal state in erase suspend word pr o g r a m (or) ef a w o r d pr o g r a m word program suspend word program busy illeg al state(is) in pg m b us y bp bus y bp suspend illegal state (is) in bp suspend illegal state (is) in bp suspend bp bp confirm if data load in program buffer is complete, else bp load 2 erase suspend is in eras e suspend otp lock efa bloc k setup re ad y re ad y ready (lock error [botch]) re ad y current chip state (8) c o m m an d in p u t to c h ip a n d resu ltin g chip next state is in b p b u s y is in pgm suspend ready (error [botch]) bp bus y word program busy word program suspend illeg al state (is) in p gm busy program suspend ready (lock error [botch]) word program busy pr o g r a m b u s y otp bus y is in o tp b usy otp bus y otp bus y otp bus y is in pgm suspend bp load 1 illegal state (is) in erase busy ready (error [botch]) re ad y ( error [botch] ) bp load 2 if w ord c ount >0, else bp c onfirm bp busy eras e (or) ef a b lo c k eras e bp suspend er a s e b u s y erase suspend re ad y ( error [botch] ) eras e bus y eras e suspend bp suspend loc k/rcr/ecr setup ready (lock error [botch]) il le g al state ( is ) in erase bus y eras e bu s y ready (lock error [botch]) is in bp bus y
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 117 table 58. next state table (sheet 2 of 6) read a rray ( 3 ) read efa word progra m (4 ,5 ,1 2 ) pr o g r a m efa write to buffered program (bp) erase setup (4 ,5 ,1 2 ) ef a b lo c k eras e setup buffered en h a n c e d factory pg m s e tu p (4,12) be confirm, blank check confirm p/e re s u me , ulb confirm (9 ) bp / pr g / era s e suspend read status clear status register (6 ) (ffh) (94h) (41h) (44h) (e9h) (20h) (24h) (80h) (d0h) (b0h) (70h) (50h) setup busy word pgm busy in ers sus word pgm busy in ers sus w ord program suspend in eras e suspend ille g a l s ta te ( is ) in pg m b u s y in eras e suspend sus pend word pr o g r a m sus pend in eras e suspend word pgm busy in ers sus word pr o g r a m suspend in erase suspend ( error bits cleared ) illegal state in word program suspend in erase suspend setup bp load 1 (10) bp load 2 (10) bp confirm bp bus y in eras e sus p end bp busy bp busy in eras e suspend bp busy in eras e suspend bp suspend in eras e suspend ille g a l s t a te ( is ) in b p b u s y in erase suspen bp suspend bp suspend in er a s e suspend bp busy in eras e suspend bp suspend in e r a s e suspend ( error bits cleared ) illegal state(is) in bp suspend in eras e suspend eras e suspend (unlock blk) setup blank check busy blank chec k busy blank chec k busy illegal state in blank check busy setup befp loadin g da ta befp busy current chip state (8) command in p ut to chi p and resultin g chip next state w ord program suspend in erase suspend word pgm busy in ers sus w ord program busy in erase sus pend bp busy in erase suspend illegal state (is) in bp busy in erase sus bp busy in erase suspend bp load 1 bp load 2 if w ord count >1, else bp confirm bp confirm if data load in program buffer is complete, else bp load 2 word program suspend in erase suspend w ord program sus pend in erase suspend w ord program busy in erase sus pend is in pgm sus in ers sus is in pgm sus in ers sus bp in erase suspend erase suspend (error [botc h bp]) erase suspend (error [botc h bp] ) is in bp sus in ers sus bp suspend in erase suspend bp busy in erase suspend loc k/rcr/ecr/lock efa block setup in erase suspend erase sus pend (lock error [botc h]) buffered enhanced fa c tory pr o g r a m mode blank check word prog ram in erase suspend (or) efa w ord prog ram in erase suspend blan k ch ec k b u s y ready (error [botc h]) erase suspend (lock error [botch]) befp program and v erify bus y (if bloc k a ddress giv en matc hes addres s given on befp setup command). commands treated as data. ( 7) blank check busy ready (error [botc h]) ready (error [botc h]) ready (error [botc h]) b la nk chec k bu s y is in blan k ch ec k b us y is in b la nk chec k bu s y bp suspend in erase suspend bp suspend in erase suspend is in bp sus in ers sus word pgm busy in ers sus is in b p bu s y in ers s us is in pgm busy in ers sus is in pgm busy in ers sus
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 118 order number: 309823, revision: 003 table 59. next state table (sheet 3 of 6) read id/q u e r y lock, unloc k, lock- dow n, rcr/ecr setup (5) loc k, unloc k, loc k-dow n lock efa blocks setup blank chec k (5) otp setup (5 ) lock block confirm (9 ) lock-dow n block confirm (9 ) write rcr/ecr confirm (9) block a ddres s ( wa0) (11) illegal cmds or befp data (2) (90h, 98h) (60h) (64h) (bch) (c0h) (01h) (2fh) (03h,04h) (xxxxh) (all other codes) ready lock/rcr/e cr setup loc k efa block setup blank chec k setup otp setup n/a ready ready (lock error [botch]) ready (lock block) ready (lock dow n blk) ready (set cr) n/a ready (lock error [botch]) ready (lock error [botch]) ready (lock block) ready (lock dow n blk) ready (lock error [botch]) n/a ready (lock error [botch]) setup busy otp busy is in o t p b u s y setup n/a w ord program bus y n/a busy word pro gra m bus y is i n w o r d pgm bu s y n/a w ord program bus y illegal state in pgm busy suspend word program suspend is i n w o r d pro gra m suspend n/a word program suspend illegal state (is) in pgm suspend setup bp load 1 bp load 2 ready (error [b o tc h ]) b p co n f ir m if d a ta lo a d in program buffer is complete, else bp load 2 bp confirm bp busy bp busy is in b p b usy n/a bp busy illegal state in bp busy bp suspend bp suspend is i n b p suspend n/a bp suspend illegal state in bp suspend setup n/a ready (error [botch]) busy eras e bus y is i n e r a s e busy n/a er a s e b u s y illegal state in erase busy suspend erase suspend lock/rcr/e cr setup in erase suspend loc k efa block setup in er a s e suspend era s e suspend is in eras e suspend n/a erase suspend illegal state in erase suspend otp otp busy bp ready otp busy otp busy otp busy is in o tp b u s y otp busy n/a ready ready ready n/a n/a n/a ready n/a lock efa block setup command in p ut to chi p a n d re su ltin g chi p next state wsm operation completes current chip state (8) ready era s e (or) efa blo c k era s e loc k/rcr/ecr setup erase suspend eras e bu s y bp suspend word program busy w ord program sus pend eras e sus pend erase suspend bp suspend illegal state (is) in erase busy erase busy ready (error [botch]) er a s e b u s y ready (error [botch]) ready (lock error [botch]) ready (lock error [botch]) word program busy bp busy ready (error [botch]) is in bp busy illegal s tate (is) in bp sus pend ready (error [botch]) bp load 1 bp confirm if data load in program buffer is complete, else bp load 2 bp load 2 if w ord count>0, else bp confirm bp suspend bp busy word program (or) efa w o rd program word program busy word program suspend word program busy illegal state (is) in w ord pgm bus y is in pgm suspend
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 119 table 60. next state table (sheet 4 of 6) rea d id / q u e r y lock, unloc k, lock- dow n, rcr/ecr setup (5 ) lock, unloc k, lock-dow n lock efa bloc ks setup blank ch ec k (5 ) otp setup (5 ) lock block confirm (9 ) lock-dow n block confirm (9 ) write rcr/ecr confirm (9 ) block a ddress ( wa0) (1 1 ) ille g a l c m d s o r b efp da ta (2 ) (90h, 98h) (60h) (64h) (bch) (c0h) (01h) (2fh) (03h,04h) (xxxxh) (all other c odes ) setup n/a w or d p rogram b usy i n eras e su s p end n/a busy word pgm busy in er s s u s is i n w o rd program busy in e ra s e suspend n/a w ord program busy in erase suspend erase suspend illegal state in pgm bus y in eras e suspend n/a w ord program busy in erase suspend is in erase suspend suspend word prog ram suspend in erase suspend is in w o r d pr o g r a m sus pend in eras e suspend n/a w ord program suspend in eras e suspend ille g a l s ta te in w o r d p r o g r a m suspend in eras e suspend n/a w ord program suspend in eras e suspend setup bp load 1 bp load 2 erase suspend (error [bo tc h b p]) b p c o n f ir m in er a s e sus pend w hen n=0, else bp load 2 bp confirm bp busy bp busy in erase suspend is in bp busy in e ra s e suspend n/a bp busy in erase suspend erase suspend illegal state in bp busy in erase suspen is in erase suspend bp suspend bp suspend in erase suspend is in b p sus pend in eras e suspend n/a bp suspend in eras e suspend illegal state in bp suspend in erase suspend n/a bp suspend in eras e suspend eras e suspend (error [bo tc h]) er a s e sus pend (l oc k b lk) eras e suspend (loc k dow n blk) erase suspend (set cr) n/a eras e sus pend (lock error [botch]) setup n/a ready (error [botch]) blank chec k busy blank check busy is in blank ch ec k bu s y n/a blank check busy illegal state in blank check busy n/a blank check busy setup n/a befp busy re ad y befp busy ready bp busy in eras e suspend bp suspend in eras e sus pend blank check busy w ord program bus y in eras e suspend w ord program bus y in eras e suspend w ord program suspend in eras e sus pend w ord program bus y in eras e suspend ready n/a blank check busy ready (error [botc h]) erase suspend (lock error [botch]) bp load 1 bp confirm if data load in program buffer is c o mplete, els e b p lo ad 2 buffered enhanc ed fac tory pr o g r a m mode befp program and v erify busy (if block a ddress given matc hes addres s given on befp setup c ommand). commands treated as data. (7) blank chec k ready (error [botch]) lock/rcr/ecr setup in eras e sus pend word program suspend in erase suspend bp suspend in erase suspend bp busy in eras e suspend ille g a l s ta te in w o r d pg m b u s y in eras e suspend is in word program suspend in erase suspend illegal state (is) in bp busy in erase sus is in bp sus in ers sus bp load 2 if w ord count>1, else bp confirm w ord program busy in erase suspend w ord program busy in erase suspend bp in erase suspend word pr o g r a m in eras e suspend (or) efa w o rd pr o g r a m in eras e suspend bp confirm in eras e sus pend w hen count=0, el s e b p lo a d 2 n/a ready (error [botc h]) ready (error [botc h]) bp suspend in eras e suspend befp program and v erify busy (if block a ddress given matches address given on befp setup command). commands treated as data. (7) word program suspend in erase suspend bp load 1 in eras e sus pend {give w ord c ount load [n-1]}; if n=0 (w ord count =1) go to bp con f irm; els e n<>0 go to b p l oa d 2 is in blank check busy bp load 2 in erase suspend (give data load) bp busy in eras e suspend eras e sus pend (error [botc h bp] ) c urrent c hip state (8) wsm operation completes c o m m a n d in p u t to c h ip a n d re s u ltin g c h ip n e x t s ta te
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 120 order number: 309823, revision: 003 table 61. next state table (sheet 5 of 6) read array ( 3 ) read efa word program setup (4,5,12) efa word program bp setup erase setup (4,5,12) efa block erase setup buffered enhanced factory pgm setup (4,12) be confirm, blank check confirm, p/e resume, ulb confirm (9) program/ erase suspend read status clear status register (6) (ffh) (94h) (41h) (44h) (e9h) (20h) (24h) (80h) (d0h) (b0h) (70h) (50h) status read status read see note 13 status read output mux does not change. efa word pgm setup, efa word pgm setup in erase susp efa block erase setup, efa block suspend efa block lock setup, efa block lock setup in erase susp lock/rcr/ecr setup, lock/rcr/ecr setup in erase susp befp setup, befp pgm & verify busy, erase setup, otp setup, bp confirm, word pgm setup, word pgm setup in erase susp, bp confirm in erase suspend blank check setup, blank check busy current chip state ready, word program busy, bp busy, erase busy, word pgm suspend, bp suspend, erase suspend, word pgm busy in erase suspend, bp suspend in erase suspend bp setup, load 1, load 2 bp setup, load1, load 2 - in erase susp. output mux does not change bp busy bp busy in erase suspend read a rra y otp busy output mux does not change. output mux does not change. read efa status read command input to chip and resulting output mux next state status read
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 121 notes: 1. the "partition data when read" field shows what the user wi ll read from the flash chip after issuing the appropriate command given the partition address is not changed from the address giv en during the command. "read-while-write" functionality gives more flexibility in data output from the device. the data read from the chip depends on the partition address applied to the device; each partition is placed into one of 3 possible output states during commands: read array, read status or read id/cfi, depending on the command given to the chip; this partition's output state is retained until a new command is given to the chip at that partition address; for example, this allows the user to set partition #1's output state to read array, and partition #4 's output state to read status; every time the partition address is changed to partition #4 (without issuing a new command), the status will be read from the chip. 2. "illegal commands" include commands outside of the allowed command set (allowed commands: 41h[pgm], 20h [erase], etc.) 3. if a "read array" is attempted from a busy partition, the result will be "indeterminate" data. the key point is that the outp ut mux for that partition will be pointing to the "array", but ?indeterminate? data will be output. when the user returns to this part ition address some time in the future, the output mux will be in the "read array" state from its last visit. "read id" and "read quer y" commands do the exact same thing in the device. the id and query data are located at different locations in the address map. 4. 1st and 2nd cycles of "2 cycles write co mmands" must be given to the same partition address, or unexpected results will occur . 5. the 2nd cycle of the following 2 cycle commands will be ignored by the user interface: program setup, erase setup, otp setup, lock/unlock/lock-down/rcr/ecr setup and blank check when issued in an "illegal condition". illegal conditions are such as "pgm setup while busy", "erase setup while busy", etc. 6. the clear status command only clears the error bits in the status register if the device is not in these modes: wsm running (pgm busy, erase busy, otp busy, befp modes); 7. befp writes are only allowed when the status register bit #0 = 0, or else the data is ignored. table 62. next state table (sheet 6 of 6) read id/query lock, unloc k, lock- dow n, rcr/ecr setup (5 ) lock, unloc k, lock-dow n lock efa blocks setup blank chec k (5) otp setup (5) lock block conf irm (9) lock-dow n block conf irm (9) write rcr/ecr conf irm (9 ) block address (wa0) illegal cmds or befp data (2) (90h, 98h) (60h) (64h) ( bch) (c0h) (01h) ( 2fh) (03h,04h) (ffffh) ( all other c odes ) status read output mux does not change. id / query read bp busy bp busy in erase suspend array read bp setup, load 1, load 2 bp setup, load1, load 2 - in erase susp. output mux will not change otp busy output mux does not change. ready, word program busy, bp busy, erase busy, word pgm suspend, bp suspend, erase suspend, word pgm busy in erase suspend, bp suspend in erase suspend efa block lock setup, efa block lock setup in erase susp loc k/rcr/ecr setup, loc k/rcr/ecr setup in eras e sus p befp setup, befp pgm & verify busy, erase setup, otp setup, bp confirm, word pgm setup, word pgm setup in erase susp, bp confirm in erase suspend blank check setup, blank check busy wsm operation completes current chip state command input to chip and resulting output mux next state output mux does not change status read efa w or d pgm se tu p , efa w or d pgm se tu p in er a s e s u s p efa block erase setup, efa block suspend status read status read status read a rray read
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 122 order number: 309823, revision: 003 8. the "current state" is that of the "chip" and not of the "partition"; each partition "remembers" which output (array, id/cfi or status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where t he partition's output mux is presently pointing to. 9. confirm commands (lock block, unlock block, lock-down block, configuration register and blank check) perform the operation and then move to the ready state. 10.buffered programming will botch when a different block addres s (as compared to address given with e8 command) is written during the bp load1 and bp load2 states 11.wa0 refers to the block address latched duri ng the first write cycle of the current operation 12.all two cycle commands will be considered as a contiguous whole during device suspend states. individual commands will not be parsed separately; that is, the second cycle of an erase command issued in program suspend will not resume the program operation. 13.for m18 108 mhz, output mux changes to read status; for m18 133 mhz, output mux does not change.
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 123 appendix f additional information order number document/tool ap-822 designing with intel strataflash ? wireless memory and pre-enabling intel strataflash ? cellular memory ap-816 effect of program buffer size on system interrupt latency ap-841 intel strataflash ? cellular memory (m18 scsp) to arm ? primecell tm design guide notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intel?s world wide web home page at http://www.intel.com for technical documentation and tools. 3. for the most current information on intel flash products, visit our website at http:// developer.intel.com/design/flash/.
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 124 order number: 309823, revision: 003 appendix g ordering information figure 68 provides the device part number decoder and table 63 provides the available combinations. for combinations not listed, please contact your local intel sales office. figure 68. m18 flash memory part number decoder 0 = no parameter blocks, non-mux interface configuration 1 = address -data multiplexed configuration f 5 0 m 0 y 0 b 8 f 4 p package pinout indicator flash density rd = leaded scsp 0 = no die 4 = 256 mbit 5 = 512 mbit b = x16d ballout c = x16c ballout 0 0 0 parameter block , interface configuration product line designator 48f = discrete flash 38f = flash + ram scsp ram density 5 = 64 mbit 6 = 128 mbit 7 = 256 mbit 8 = 512 mbit 0 = no die i/o voltage option , flash ce # configuration y = 1.8 volt core and i/o, individual flash ce # device details 0 = original released version . flash #1 flash #2 ram #1 ram #2 flash family 1 flash family 2 product family m = m18 flash memory 0 = no die pf = pb-free scsp
intel strataflash ? cellular memory datasheet intel strataflash ? cellular memory (m18) 23-feb-2006 order number: 309823, revision: 003 125 note: to order any of the parts listed above and to obtain a datasheet for the m18 scsp parts, please contact your local intel sales office. table 63. package ordering information i/o voltage flash component ram component package part order number (v) density in mbit and family density in mbit and type size (mm) ball type type non-mux, x16c 1.8 256 non-mux 64 psram 8 x 11 x 1.2 x16c 107-ball lead-free pf38f4050m0y0c0 1.8 512 non-mux 64 psram 8 x 11 x 1.2 x16c 107-ball lead-free pf38f5050m0y0c0 1.8 512 non-mux 128 psram 8 x 11 x 1.2 x16c 107-ball lead-free pf38f5060m0y0c0 1.8 512 + 512 non-mux 128 + 128 psram 8 x 11 x 1.4 x16c 107-ball lead-free pf38f5566mmy0c0 non-mux, x16d 1.8 512 non-mux 128 lpsdram 9 x 11 x 1.2 x16d 105-ball lead-free PF38F5060M0Y0B0 1.8 512 non-mux 256 lpsdram 9 x 11 x 1.2 x16d 105-ball lead-free pf38f5070m0y0b0 1.8 512 + 512 non-mux n/a 8 x 10 x 1.4 x16d 105-ball lead-free pf48f5500m0y0b0 mux, x16d 1.8 512 + 512 mux n/a 8 x 10 x 1.4 x16d 105-ball lead-free pf48f5500m0y1b0
intel strataflash ? cellular memory 23-feb-2006 intel strataflash ? cellular memory (m18) datasheet 126 order number: 309823, revision: 003

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